i915/display/intel_dpll.c

237 /* LVDS 100mhz refclk limits. */
316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
322 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
340 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
353 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
360 int chv_calc_dpll_params(int refclk, struct dpll *clock)
366 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
429 	int refclk = i9xx_pll_refclk(crtc_state);
470 			port_clock = pnv_calc_dpll_params(refclk, &clock);
472 			port_clock = i9xx_calc_dpll_params(refclk, &clock);
501 		port_clock = i9xx_calc_dpll_params(refclk, &clock);
519 	int refclk = 100000;
537 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
549 	int refclk = 100000;
571 	crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
575  * Returns whether the given set of divisors are valid for a given refclk with
640  * refclk, or FALSE.
650 		    int target, int refclk,
674 					i9xx_calc_dpll_params(refclk, &clock);
698  * refclk, or FALSE.
708 		   int target, int refclk,
730 					pnv_calc_dpll_params(refclk, &clock);
754  * refclk, or FALSE.
764 		   int target, int refclk,
791 					i9xx_calc_dpll_params(refclk, &clock);
853  * refclk, or FALSE.
858 		   int target, int refclk,
867 	int max_n = min(limit->n.max, refclk / 19200);
883 								     refclk * clock.m1);
885 					vlv_calc_dpll_params(refclk, &clock);
911  * refclk, or FALSE.
916 		   int target, int refclk,
932 	 * set to 2.  If requires to support 200Mhz refclk, we need to
947 						   refclk * clock.m1);
954 			chv_calc_dpll_params(refclk, &clock);
976 	int refclk = 100000;
979 				  crtc_state->port_clock, refclk,
1359 	int refclk = 120000;
1371 			refclk = dev_priv->display.vbt.lvds_ssc_freq;
1375 			if (refclk == 100000)
1380 			if (refclk == 100000)
1391 				refclk, NULL, &crtc_state->dpll))
1394 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1480 	int refclk = 100000;
1484 				refclk, NULL, &crtc_state->dpll))
1487 	chv_calc_dpll_params(refclk, &crtc_state->dpll);
1507 	int refclk = 100000;
1511 				refclk, NULL, &crtc_state->dpll))
1514 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1535 	int refclk = 96000;
1539 			refclk = dev_priv->display.vbt.lvds_ssc_freq;
1542 				    refclk);
1561 				refclk, NULL, &crtc_state->dpll))
1564 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1584 	int refclk = 96000;
1588 			refclk = dev_priv->display.vbt.lvds_ssc_freq;
1591 				    refclk);
1601 				refclk, NULL, &crtc_state->dpll))
1604 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1622 	int refclk = 96000;
1626 			refclk = dev_priv->display.vbt.lvds_ssc_freq;
1629 				    refclk);
1639 				 refclk, NULL, &crtc_state->dpll))
1642 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1662 	int refclk = 48000;
1666 			refclk = dev_priv->display.vbt.lvds_ssc_freq;
1669 				    refclk);
1681 				 refclk, NULL, &crtc_state->dpll))
1684 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
2052 	/* Feedback refclk divider - n and m1 */