i915/display/intel_dpio_phy.c

44  * adds another PHY for driving port D. Each PHY responds to specific
45  * IOSF-SB port.
71  * the spline (PCS/TX) corresponds to the port.
79  *  port B == PCS/TX CH0
81  *  port C == PCS/TX CH1
84  * ie. drive port B with pipe B, or port C with pipe A.
90  *  port D == PCS/TX CH0
92  * On BXT the entire PHY channel corresponds to the port. That means
93  * the PLL is also now associated with the port rather than the pipe,
95  * Port A PLL is directly connected to transcoder EDP and port B/C
98  * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
99  * digital port D (CHV) or port A (BXT). ::
123  *     |     DDI2      | DP/HDMI port
160 		 * @channel.port: which port maps to this channel.
162 		enum port port;
173 			[DPIO_CH0] = { .port = PORT_B },
174 			[DPIO_CH1] = { .port = PORT_C },
183 			[DPIO_CH0] = { .port = PORT_A },
196 			[DPIO_CH0] = { .port = PORT_B },
206 			[DPIO_CH0] = { .port = PORT_A },
216 			[DPIO_CH0] = { .port = PORT_C },
243 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
254 		if (port == phy_info->channel[DPIO_CH0].port) {
261 		    port == phy_info->channel[DPIO_CH1].port) {
269 		 port_name(port));
305 	bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
618 	enum port port = encoder->port;
623 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
640 	enum port port = encoder->port;
646 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
662 	switch (dig_port->base.port) {
664 		MISSING_CASE(dig_port->base.port);
676 	switch (dig_port->base.port) {
678 		MISSING_CASE(dig_port->base.port);
926 	 * pick the CL based on the port.
1054 	 * When the port is off and the override is removed
1132 	/* Enable clock channels for this port */