i915/display/intel_dpio_phy.c

128  * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy
132 	 * @dual_channel: true if this phy has a second channel.
137 	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
138 	 * Otherwise the GRC value will be copied from the phy indicated by
145 	 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
151 	 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
234 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
240 	return &phy_list[phy];
244 			     enum dpio_phy *phy, enum dpio_channel *ch)
255 			*phy = i;
262 			*phy = i;
270 	*phy = DPIO_PHY0;
298 	enum dpio_phy phy;
305 	bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
311 	bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
312 			     BXT_PORT_PCS_DW10_GRP(phy, ch),
318 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
328 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
333 		val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
342 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
347 	bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
348 			     BXT_PORT_PCS_DW10_GRP(phy, ch),
353 			     enum dpio_phy phy)
357 	phy_info = bxt_get_phy_info(dev_priv, phy);
362 	if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
365 			"DDI PHY %d powered, but power hasn't settled\n", phy);
370 	if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
372 			"DDI PHY %d powered, but still in reset\n", phy);
380 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
382 	u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
388 				  enum dpio_phy phy)
390 	if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
393 			phy);
397 			       enum dpio_phy phy)
402 	phy_info = bxt_get_phy_info(dev_priv, phy);
404 	if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
407 			dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
409 		if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
411 				"won't reprogram it\n", phy);
417 			"force reprogramming it\n", phy);
430 	if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
433 			phy);
436 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
439 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
443 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
447 		intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
466 		intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
467 		intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
474 	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
477 void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
481 	phy_info = bxt_get_phy_info(dev_priv, phy);
483 	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
488 void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
491 		bxt_get_phy_info(dev_priv, phy);
508 	_bxt_dpio_phy_init(dev_priv, phy);
515 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
533 			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
542 			       enum dpio_phy phy)
548 	phy_info = bxt_get_phy_info(dev_priv, phy);
551 	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
554 	if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
560 	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
562 		   "BXT_PORT_CL1CM_DW9(%d)", phy);
563 	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
565 		   "BXT_PORT_CL1CM_DW10(%d)", phy);
569 	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
570 		   "BXT_PORT_CL1CM_DW28(%d)", phy);
573 		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
575 			   "BXT_PORT_CL2CM_DW6(%d)", phy);
585 		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
586 			   "BXT_PORT_REF_DW6(%d)", phy);
589 		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
590 			   "BXT_PORT_REF_DW8(%d)", phy);
619 	enum dpio_phy phy;
623 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
630 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
641 	enum dpio_phy phy;
646 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
651 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
724 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
731 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
735 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
738 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
742 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
745 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch));
748 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val);
751 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch));
754 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val);
759 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));
762 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);
767 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));
780 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);
790 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i));
795 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val);
799 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
801 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
804 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
806 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
819 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
822 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
827 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val);
830 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch));
835 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val);
838 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch));
844 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val);
847 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch));
853 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val);
864 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
887 		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
893 		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
895 		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
901 		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
905 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));
911 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);
914 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));
920 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);
928 	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));
933 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);
945 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
952 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
954 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
957 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
959 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
969 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data);
984 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
986 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
989 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
991 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
994 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch),
1002 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch),
1031 	enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1039 		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
1041 		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
1043 		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
1045 		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
1070 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
1074 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
1075 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
1076 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
1078 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
1081 		vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
1083 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
1084 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
1085 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
1096 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
1101 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
1104 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
1111 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
1112 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
1113 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
1126 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
1137 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
1140 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
1141 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
1152 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
1155 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
1156 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);