i915/display/intel_dpio_phy.c

244 			     enum dpio_phy *phy, enum dpio_channel *ch)
256 			*ch = DPIO_CH0;
263 			*ch = DPIO_CH1;
271 	*ch = DPIO_CH0;
297 	enum dpio_channel ch;
305 	bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
311 	bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
312 			     BXT_PORT_PCS_DW10_GRP(phy, ch),
318 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
328 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
333 		val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
342 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
347 	bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
348 			     BXT_PORT_PCS_DW10_GRP(phy, ch),
620 	enum dpio_channel ch;
623 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
630 		intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
642 	enum dpio_channel ch;
646 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
651 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
723 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
731 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
735 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
738 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
742 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
745 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch));
748 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val);
751 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch));
754 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val);
759 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));
762 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);
767 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));
780 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);
790 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i));
795 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val);
799 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
801 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
804 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
806 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
818 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
822 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
827 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val);
830 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch));
835 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val);
838 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch));
844 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val);
847 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch));
853 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val);
863 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
874 	if (ch == DPIO_CH0 && pipe == PIPE_B)
889 		if (ch == DPIO_CH0)
891 		if (ch == DPIO_CH1)
897 		if (ch == DPIO_CH0)
899 		if (ch == DPIO_CH1)
905 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));
911 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);
914 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));
920 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);
928 	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));
933 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);
944 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
952 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
954 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
957 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
959 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
969 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data);
984 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
986 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
989 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
991 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
994 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch),
1002 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch),
1069 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
1074 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
1075 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
1076 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
1078 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
1081 		vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
1083 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
1084 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
1085 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
1095 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
1101 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
1104 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
1111 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
1112 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
1113 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
1125 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
1137 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
1140 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
1141 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
1151 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
1155 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
1156 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);