i915/display/intel_dp_link_training.c

344 						 const u8 link_status[DP_LINK_STATUS_SIZE],
351 		tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
354 			tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
364 						  const u8 link_status[DP_LINK_STATUS_SIZE],
375 		v = drm_dp_get_adjust_request_voltage(link_status, lane);
376 		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
379 			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
380 			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
400 					 const u8 link_status[DP_LINK_STATUS_SIZE],
405 							      dp_phy, link_status, lane);
408 							       dp_phy, link_status, lane);
412 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
413 	(drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
414 #define TRAIN_REQ_VSWING_ARGS(link_status) \
415 	_TRAIN_REQ_VSWING_ARGS(link_status, 0), \
416 	_TRAIN_REQ_VSWING_ARGS(link_status, 1), \
417 	_TRAIN_REQ_VSWING_ARGS(link_status, 2), \
418 	_TRAIN_REQ_VSWING_ARGS(link_status, 3)
419 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
420 	(drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
421 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \
422 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
423 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
424 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
425 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
426 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \
427 	drm_dp_get_adjust_tx_ffe_preset((link_status), (lane))
428 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \
429 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
430 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
431 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
432 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
438 			  const u8 link_status[DP_LINK_STATUS_SIZE])
447 		       TRAIN_REQ_TX_FFE_ARGS(link_status));
454 		       TRAIN_REQ_VSWING_ARGS(link_status),
455 		       TRAIN_REQ_PREEMPH_ARGS(link_status));
461 						       dp_phy, link_status, lane);
781 			  const u8 link_status[DP_LINK_STATUS_SIZE])
785 	       link_status[0], link_status[1], link_status[2],
786 	       link_status[3], link_status[4], link_status[5]);
800 	u8 link_status[DP_LINK_STATUS_SIZE];
834 						     link_status) < 0) {
839 		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
845 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
851 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
858 					  link_status);
864 		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
869 		memcpy(old_link_status, link_status, sizeof(link_status));
875 	intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
951 	u8 link_status[DP_LINK_STATUS_SIZE];
975 						     link_status) < 0) {
981 		if (!drm_dp_clock_recovery_ok(link_status,
983 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
989 		if (drm_dp_channel_eq_ok(link_status,
998 					  link_status);
1007 		intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
1153 	u8 link_status[DP_LINK_STATUS_SIZE];
1174 	if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1180 	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1205 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1210 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1211 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1217 		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
1223 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1232 		intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1240 		intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1249 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1254 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1255 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1260 		if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {
1266 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1285 	u8 link_status[DP_LINK_STATUS_SIZE];
1305 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1310 		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
1311 		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
1312 		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
1317 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1318 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1324 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);