i915/display/intel_dp.c

443 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
445 	return DISPLAY_VER(dev_priv) >= 12 ||
446 		(DISPLAY_VER(dev_priv) == 11 &&
528 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
533 	drm_WARN_ON(&dev_priv->drm,
536 	if (DISPLAY_VER(dev_priv) >= 14) {
540 	} else if (DISPLAY_VER(dev_priv) >= 11) {
543 		if (IS_DG2(dev_priv))
545 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
546 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
548 		else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
552 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
555 	} else if (DISPLAY_VER(dev_priv) == 9) {
558 	} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
559 		   IS_BROADWELL(dev_priv)) {
1096 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1112 	return hdisplay == 4096 && !HAS_DDI(dev_priv);
1226 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1230 	int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1236 	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1263 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1274 	if (HAS_DSC(dev_priv) &&
1299 				intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1317 	if (intel_dp_joiner_needs_dsc(dev_priv, bigjoiner) && !dsc)
1327 	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1424 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1426 	if (DISPLAY_VER(dev_priv) >= 12)
1429 	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1491 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1517 			drm_dbg_kms(&dev_priv->drm,
2198 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2229 			drm_dbg_kms(&dev_priv->drm,
2241 			drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2254 			drm_dbg_kms(&dev_priv->drm,
2271 		drm_dbg_kms(&dev_priv->drm,
2280 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2519 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2522 	if (IS_G4X(dev_priv))
2524 	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2535 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2612 	drm_WARN_ON(&dev_priv->drm,
2697 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2706 		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2901 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2909 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2929 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2969 		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2994 	if (!HAS_DDI(dev_priv))
3587 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3602 		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3607 			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3609 		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3865 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3883 		drm_dbg_kms(&dev_priv->drm,
3929 	struct drm_i915_private *dev_priv =
3933 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3953 		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4005 	if (HAS_DSC(dev_priv))
4315 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4328 		len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4341 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
4352 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4358 	if (HAS_AS_SDP(dev_priv))
4361 	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4364 	if (!enable && HAS_DSC(dev_priv))
4371 	intel_de_write(dev_priv, reg, val);
4372 	intel_de_posting_read(dev_priv, reg);
4490 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4504 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4558 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4572 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4580 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4596 		drm_dbg_kms(&dev_priv->drm,
4772 	struct drm_i915_private *dev_priv =
4783 		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4784 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4785 		if (DISPLAY_VER(dev_priv) >= 10)
4786 			intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4791 		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4792 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4796 		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4797 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4802 		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4803 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4812 		drm_dbg_kms(&dev_priv->drm,
4815 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4817 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4819 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4820 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4830 		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4832 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4837 		if (DISPLAY_VER(dev_priv) < 10)  {
4838 			drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4841 		drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4842 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4843 		intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4848 		drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
5215 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5224 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5242 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5245 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5250 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5252 			intel_set_pch_fifo_underrun_reporting(dev_priv,
5256 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5261 		if (DISPLAY_VER(dev_priv) >= 12 &&
5273 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5280 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5282 			intel_set_pch_fifo_underrun_reporting(dev_priv,
5339 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5345 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5357 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5360 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5365 		if (DISPLAY_VER(dev_priv) >= 12 &&
5469 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5507 		drm_dbg_kms(&dev_priv->drm,
5510 		drm_kms_helper_hotplug_event(&dev_priv->drm);
5513 		drm_dbg_kms(&dev_priv->drm,
5621 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5627 	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5829 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
5838 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5840 	drm_WARN_ON(&dev_priv->drm,
5841 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5843 	if (!intel_display_device_enabled(dev_priv))
5846 	if (!intel_display_driver_check_access(dev_priv))
5947 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5949 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5952 	if (!intel_display_driver_check_access(dev_priv))
6093 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6098 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6134 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6140 	for_each_intel_crtc(&dev_priv->drm, crtc) {
6167 	drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6201 	struct drm_i915_private *dev_priv = to_i915(conn->dev);
6231 	if (DISPLAY_VER(dev_priv) < 9)
6339 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6347 	if (DISPLAY_VER(dev_priv) < 5)
6350 	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6389 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
6395 	if (!IS_G4X(dev_priv) && port != PORT_A)
6399 	if (HAS_GMCH(dev_priv))
6401 	else if (DISPLAY_VER(dev_priv) >= 5)
6415 	if (HAS_VRR(dev_priv))
6462 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6478 	if (intel_get_lvds_encoder(dev_priv)) {
6479 		drm_WARN_ON(&dev_priv->drm,
6480 			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6481 		drm_info(&dev_priv->drm,
6487 	intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6491 		drm_info(&dev_priv->drm,
6516 		drm_info(&dev_priv->drm,
6539 			drm_info(&dev_priv->drm,
6551 		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6554 			drm_info(&dev_priv->drm,
6561 	mutex_lock(&dev_priv->drm.mode_config.mutex);
6567 			drm_dbg_kms(&dev_priv->drm,
6582 	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6598 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
6601 		drm_info(&dev_priv->drm,
6662 	struct drm_i915_private *dev_priv = to_i915(dev);
6680 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6683 	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6693 		if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6694 				      IS_CHERRYVIEW(dev_priv)) &&
6704 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6710 	drm_dbg_kms(&dev_priv->drm,
6719 	if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6727 	if (HAS_DDI(dev_priv))
6748 	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6751 			drm_dbg_kms(&dev_priv->drm,
6766 	intel_display_power_flush_work(dev_priv);
6772 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6776 	if (!HAS_DISPLAY(dev_priv))
6779 	for_each_intel_encoder(&dev_priv->drm, encoder) {
6795 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6799 	if (!HAS_DISPLAY(dev_priv))
6802 	for_each_intel_encoder(&dev_priv->drm, encoder) {