i915/display/intel_dp.c

387  * The required data bandwidth for a mode with given pixel clock and bpp. This
735 	 * TODO: Calculate the actual overhead for a given mode.
738 	 * 0.453% DSC overhead. This is enough for a 3840 width mode,
740 	 * enough for a 1024 width mode where this is ~0.8% (on a 4
778 		 * that and probably means we can't fit the required mode, even with
842 	 * for MST -> TimeSlots has to be calculated, based on mode requirements
845 	 * To support the given mode:
1073 		     const struct drm_display_mode *mode)
1077 	if (drm_mode_is_420_only(info, mode))
1085 			     const struct drm_display_mode *mode)
1089 	sink_format = intel_dp_sink_format(connector, mode);
1155 			       const struct drm_display_mode *mode,
1167 		int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1186 	sink_format = intel_dp_sink_format(connector, mode);
1195 		    !drm_mode_is_420_also(info, mode))
1222 		    struct drm_display_mode *mode)
1228 	int target_clock = mode->clock;
1236 	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1240 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1243 	if (mode->clock < 10000)
1246 	fixed_mode = intel_panel_fixed_mode(connector, mode);
1248 		status = intel_panel_mode_valid(connector, mode);
1256 				    mode->hdisplay, target_clock)) {
1263 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1272 					   intel_dp_mode_min_output_bpp(connector, mode));
1279 		sink_format = intel_dp_sink_format(connector, mode);
1303 								    mode->hdisplay,
1310 							     mode->hdisplay,
1323 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1327 	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1471 	 * out of spec mode they will have to be satisfied with 8bpc.
2230 				    "No Valid pipe bpp for given mode ret = %d\n", ret);
2293  * @dsc: DSC compression mode
2297  * pipe bpp range, @crtc_state and @dsc mode.
2633 	/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
2636 	as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
2823 			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3281 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3291 	if (mode != DP_SET_POWER_D0) {
3295 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3310 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3323 			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
3569 	/* Set PCON source control mode */
3600 		int ret, mode;
3602 		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3604 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3606 		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3607 			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3728 		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3764 			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3771 			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3839 				     struct drm_display_mode *mode)
3846 	if (!mode || !n)
3849 	mode->hdisplay = (mode->hdisplay - overlap) * n;
3850 	mode->hsync_start = (mode->hsync_start - overlap) * n;
3851 	mode->hsync_end = (mode->hsync_end - overlap) * n;
3852 	mode->htotal = (mode->htotal - overlap) * n;
3853 	mode->clock *= n;
3855 	drm_mode_set_name(mode);
3858 		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3860 		    DRM_MODE_ARG(mode));
3873 		 * Some machines in UEFI boot mode provide us a VBT that has 18
3880 		 * up by the BIOS, and thus we can't get the mode at module
4224 	sdp->db[0] = as_sdp->mode;
4407 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4738 		 * Use failsafe mode for all cases
5087 		/* Restart FRL training or fall back to TMDS mode */
5884 	 * TODO: Reset link params when switching to MST mode, until MST
5896 		 * If we are in MST mode then this connector
5971 	/* Also add fixed mode, which may or may not be present in EDID */
5980 		struct drm_display_mode *mode;
5982 		mode = drm_dp_downstream_mode(connector->dev,
5985 		if (mode) {
5986 			drm_mode_probed_add(connector, mode);
6590 	/* multiply the mode clock and horizontal timings for MSO */
6602 			 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",