i915/display/intel_dp.c

134 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
174 	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
182 	return drm_dp_max_lane_count(intel_dp->dpcd);
191 /* update sink rates from dpcd */
228 	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
971 	if (!drm_dp_is_branch(intel_dp->dpcd))
988 	if (!drm_dp_is_branch(intel_dp->dpcd))
1026 		    (!drm_dp_is_branch(intel_dp->dpcd) ||
2953 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3064 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3065 		drm_dp_is_branch(intel_dp->dpcd) &&
3288 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3347 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3555 	if (drm_dp_is_branch(intel_dp->dpcd) &&
3718 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3721 	if (!drm_dp_is_branch(intel_dp->dpcd))
3907 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3914 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3933 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3935 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3939 			 drm_dp_is_branch(intel_dp->dpcd));
4025 					  intel_dp->dpcd,
4050 				 drm_dp_is_branch(intel_dp->dpcd));
4078 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4105 	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4119 	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4878 				    intel_dp->dpcd[DP_DPCD_REV]);
5406 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5431 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5483 	 * the value that was stored earlier or dpcd read failed
5533 	u8 *dpcd = intel_dp->dpcd;
5547 	if (!drm_dp_is_branch(dpcd))
5565 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5571 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5678 		drm_dp_downstream_max_bpc(intel_dp->dpcd,
5682 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5686 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5690 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5695 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5714 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5735 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5740 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5743 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5820 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5936 						 intel_dp->dpcd,
5983 					      intel_dp->dpcd,
6290 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
6322 		intel_dp_read_dprx_caps(intel_dp, dpcd);
6551 		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6552 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==