i915/display/intel_display_wa.c

11 static void gen11_display_wa_apply(struct drm_i915_private *i915)
14 	intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
18 	intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
21 static void xe_d_display_wa_apply(struct drm_i915_private *i915)
24 	intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
28 	intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
31 static void adlp_display_wa_apply(struct drm_i915_private *i915)
34 	intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
37 	intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
40 void intel_display_wa_apply(struct drm_i915_private *i915)
42 	if (IS_ALDERLAKE_P(i915))
43 		adlp_display_wa_apply(i915);
44 	else if (DISPLAY_VER(i915) == 12)
45 		xe_d_display_wa_apply(i915);
46 	else if (DISPLAY_VER(i915) == 11)
47 		gen11_display_wa_apply(i915);