Lines Matching refs:dev_priv
26 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
28 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
35 * @dev_priv: driver private
39 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
44 lockdep_assert_held(&dev_priv->irq_lock);
45 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
47 new_val = dev_priv->irq_mask;
51 if (new_val != dev_priv->irq_mask &&
52 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
53 dev_priv->irq_mask = new_val;
54 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
55 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
71 * @dev_priv: driver private
75 void bdw_update_port_irq(struct drm_i915_private *dev_priv,
81 lockdep_assert_held(&dev_priv->irq_lock);
83 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
85 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
88 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
95 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
96 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
102 * @dev_priv: driver private
107 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
113 lockdep_assert_held(&dev_priv->irq_lock);
115 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
117 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
120 new_val = dev_priv->display.irq.de_irq_mask[pipe];
124 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) {
125 dev_priv->display.irq.de_irq_mask[pipe] = new_val;
126 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe),
127 dev_priv->display.irq.de_irq_mask[pipe]);
128 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
146 * @dev_priv: driver private
150 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
154 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
159 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
161 lockdep_assert_held(&dev_priv->irq_lock);
163 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
166 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
167 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
180 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
183 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe];
186 lockdep_assert_held(&dev_priv->irq_lock);
188 if (DISPLAY_VER(dev_priv) < 5)
195 if (drm_WARN_ON_ONCE(&dev_priv->drm,
202 if (drm_WARN_ON_ONCE(&dev_priv->drm,
215 drm_WARN_ONCE(&dev_priv->drm,
224 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
230 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
234 lockdep_assert_held(&dev_priv->irq_lock);
235 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
237 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)
240 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
241 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
243 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
244 intel_uncore_posting_read(&dev_priv->uncore, reg);
247 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
253 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
257 lockdep_assert_held(&dev_priv->irq_lock);
258 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
260 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0)
263 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
264 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
266 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
267 intel_uncore_posting_read(&dev_priv->uncore, reg);
280 * @dev_priv: i915 device private
282 void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
284 if (!i915_has_asle(dev_priv))
287 spin_lock_irq(&dev_priv->irq_lock);
289 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
290 if (DISPLAY_VER(dev_priv) >= 4)
291 i915_enable_pipestat(dev_priv, PIPE_A,
294 spin_unlock_irq(&dev_priv->irq_lock);
298 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
304 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
320 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
333 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
355 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
358 display_pipe_crc_irq_handler(dev_priv, pipe,
359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
363 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
366 display_pipe_crc_irq_handler(dev_priv, pipe,
367 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
368 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
369 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
370 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
371 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
374 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
379 if (DISPLAY_VER(dev_priv) >= 3)
380 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
384 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
385 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
389 display_pipe_crc_irq_handler(dev_priv, pipe,
390 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
391 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
392 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
396 void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
400 for_each_pipe(dev_priv, pipe) {
401 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
405 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0;
409 void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
414 spin_lock(&dev_priv->irq_lock);
416 if (!dev_priv->display.irq.display_irqs_enabled) {
417 spin_unlock(&dev_priv->irq_lock);
421 for_each_pipe(dev_priv, pipe) {
449 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe];
455 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
456 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
468 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
469 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
472 spin_unlock(&dev_priv->irq_lock);
475 void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
480 for_each_pipe(dev_priv, pipe) {
482 intel_handle_vblank(dev_priv, pipe);
485 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
488 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
492 void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
498 for_each_pipe(dev_priv, pipe) {
500 intel_handle_vblank(dev_priv, pipe);
506 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
509 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
513 intel_opregion_asle_intr(dev_priv);
516 void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
522 for_each_pipe(dev_priv, pipe) {
524 intel_handle_vblank(dev_priv, pipe);
530 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
533 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
537 intel_opregion_asle_intr(dev_priv);
540 intel_gmbus_irq_handler(dev_priv);
543 void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
548 for_each_pipe(dev_priv, pipe) {
550 intel_handle_vblank(dev_priv, pipe);
553 flip_done_handler(dev_priv, pipe);
556 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
559 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
563 intel_gmbus_irq_handler(dev_priv);
566 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
571 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
576 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
581 intel_dp_aux_irq_handler(dev_priv);
584 intel_gmbus_irq_handler(dev_priv);
587 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
590 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
593 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
596 for_each_pipe(dev_priv, pipe)
597 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
599 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
603 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
606 drm_dbg(&dev_priv->drm,
610 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
613 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
616 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
618 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
622 drm_err(&dev_priv->drm, "Poison interrupt\n");
624 for_each_pipe(dev_priv, pipe) {
626 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
629 if (IS_IVYBRIDGE(dev_priv))
630 ivb_pipe_crc_irq_handler(dev_priv, pipe);
632 hsw_pipe_crc_irq_handler(dev_priv, pipe);
636 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
639 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
641 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
645 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
647 for_each_pipe(dev_priv, pipe)
649 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
651 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
654 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
659 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
664 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
669 intel_dp_aux_irq_handler(dev_priv);
672 intel_gmbus_irq_handler(dev_priv);
675 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
678 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
681 for_each_pipe(dev_priv, pipe)
682 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
684 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
688 cpt_serr_int_handler(dev_priv);
691 void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
697 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
700 intel_dp_aux_irq_handler(dev_priv);
703 intel_opregion_asle_intr(dev_priv);
706 drm_err(&dev_priv->drm, "Poison interrupt\n");
708 for_each_pipe(dev_priv, pipe) {
710 intel_handle_vblank(dev_priv, pipe);
713 flip_done_handler(dev_priv, pipe);
716 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
719 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
724 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
726 if (HAS_PCH_CPT(dev_priv))
727 cpt_irq_handler(dev_priv, pch_iir);
729 ibx_irq_handler(dev_priv, pch_iir);
732 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
735 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
736 gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
739 void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
745 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
748 ivb_err_int_handler(dev_priv);
753 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
757 psr_iir = intel_uncore_rmw(&dev_priv->uncore,
765 intel_dp_aux_irq_handler(dev_priv);
768 intel_opregion_asle_intr(dev_priv);
770 for_each_pipe(dev_priv, pipe) {
772 intel_handle_vblank(dev_priv, pipe);
775 flip_done_handler(dev_priv, pipe);
779 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
780 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
782 cpt_irq_handler(dev_priv, pch_iir);
785 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
789 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
793 if (DISPLAY_VER(dev_priv) >= 20)
795 else if (DISPLAY_VER(dev_priv) >= 14)
798 else if (DISPLAY_VER(dev_priv) >= 13)
808 else if (DISPLAY_VER(dev_priv) >= 12)
820 if (DISPLAY_VER(dev_priv) >= 9)
825 if (DISPLAY_VER(dev_priv) == 11) {
833 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
835 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
837 else if (DISPLAY_VER(dev_priv) >= 11)
839 else if (DISPLAY_VER(dev_priv) >= 9)
845 static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
847 wake_up_all(&dev_priv->display.pmdemand.waitqueue);
851 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
855 if (DISPLAY_VER(dev_priv) >= 14) {
859 drm_dbg(&dev_priv->drm,
862 intel_pmdemand_irq_handler(dev_priv);
866 intel_opregion_asle_intr(dev_priv);
875 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
878 if (DISPLAY_VER(dev_priv) >= 12)
883 psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0);
891 if (DISPLAY_VER(dev_priv) < 12)
897 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);
900 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
912 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
924 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
928 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
933 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
945 drm_err(&dev_priv->drm, "Invalid PIPE\n");
949 intel_handle_vblank(dev_priv, pipe);
953 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0);
964 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
968 if (DISPLAY_VER(dev_priv) >= 13)
1003 void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
1008 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
1011 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
1013 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
1014 gen8_de_misc_irq_handler(dev_priv, iir);
1016 drm_err_ratelimited(&dev_priv->drm,
1021 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
1022 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
1024 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
1025 gen11_hpd_irq_handler(dev_priv, iir);
1027 drm_err_ratelimited(&dev_priv->drm,
1033 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
1037 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
1039 if (iir & gen8_de_port_aux_mask(dev_priv)) {
1040 intel_dp_aux_irq_handler(dev_priv);
1044 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1048 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
1051 } else if (IS_BROADWELL(dev_priv)) {
1055 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
1060 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1062 intel_gmbus_irq_handler(dev_priv);
1066 if (DISPLAY_VER(dev_priv) >= 11) {
1070 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
1076 drm_err_ratelimited(&dev_priv->drm,
1079 drm_err_ratelimited(&dev_priv->drm,
1084 for_each_pipe(dev_priv, pipe) {
1090 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
1092 drm_err_ratelimited(&dev_priv->drm,
1097 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
1100 intel_handle_vblank(dev_priv, pipe);
1102 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
1103 flip_done_handler(dev_priv, pipe);
1106 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1108 if (iir & gen8_de_pipe_underrun_mask(dev_priv))
1109 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1111 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
1113 drm_err_ratelimited(&dev_priv->drm,
1119 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
1128 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);
1131 xelpdp_pica_irq_handler(dev_priv, pica_iir);
1133 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
1134 icp_irq_handler(dev_priv, iir);
1135 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
1136 spt_irq_handler(dev_priv, iir);
1138 cpt_irq_handler(dev_priv, iir);
1144 drm_dbg(&dev_priv->drm,
1194 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1198 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1199 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
1200 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1223 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1227 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1228 i915_enable_pipestat(dev_priv, pipe,
1230 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1237 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1240 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
1243 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1244 ilk_enable_display_irq(dev_priv, bit);
1245 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1250 if (HAS_PSR(dev_priv))
1259 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1272 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT,
1275 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0);
1283 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1290 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1291 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
1292 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1297 if (HAS_PSR(dev_priv))
1308 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1312 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1313 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
1314 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1329 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1333 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1334 i915_disable_pipestat(dev_priv, pipe,
1336 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1341 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1344 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
1347 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1348 ilk_disable_display_irq(dev_priv, bit);
1349 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1355 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1362 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1363 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
1364 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1367 void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
1369 struct intel_uncore *uncore = &dev_priv->uncore;
1371 if (IS_CHERRYVIEW(dev_priv))
1376 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
1379 i9xx_pipestat_irq_reset(dev_priv);
1382 dev_priv->irq_mask = ~0u;
1385 void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
1387 struct intel_uncore *uncore = &dev_priv->uncore;
1395 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
1396 for_each_pipe(dev_priv, pipe)
1397 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
1405 if (IS_CHERRYVIEW(dev_priv))
1409 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
1411 dev_priv->irq_mask = ~enable_mask;
1413 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
1416 void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
1418 struct intel_uncore *uncore = &dev_priv->uncore;
1421 if (!HAS_DISPLAY(dev_priv))
1427 for_each_pipe(dev_priv, pipe)
1428 if (intel_display_power_is_enabled(dev_priv,
1436 void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
1438 struct intel_uncore *uncore = &dev_priv->uncore;
1443 if (!HAS_DISPLAY(dev_priv))
1448 if (DISPLAY_VER(dev_priv) >= 12) {
1451 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
1455 if (!intel_display_power_is_enabled(dev_priv, domain))
1466 for_each_pipe(dev_priv, pipe)
1467 if (intel_display_power_is_enabled(dev_priv,
1474 if (DISPLAY_VER(dev_priv) >= 14)
1479 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
1483 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1486 struct intel_uncore *uncore = &dev_priv->uncore;
1488 gen8_de_pipe_underrun_mask(dev_priv) |
1489 gen8_de_pipe_flip_done_mask(dev_priv);
1492 spin_lock_irq(&dev_priv->irq_lock);
1494 if (!intel_irqs_enabled(dev_priv)) {
1495 spin_unlock_irq(&dev_priv->irq_lock);
1499 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1501 dev_priv->display.irq.de_irq_mask[pipe],
1502 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);
1504 spin_unlock_irq(&dev_priv->irq_lock);
1507 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1510 struct intel_uncore *uncore = &dev_priv->uncore;
1513 spin_lock_irq(&dev_priv->irq_lock);
1515 if (!intel_irqs_enabled(dev_priv)) {
1516 spin_unlock_irq(&dev_priv->irq_lock);
1520 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1523 spin_unlock_irq(&dev_priv->irq_lock);
1526 intel_synchronize_irq(dev_priv);
1540 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
1542 struct intel_uncore *uncore = &dev_priv->uncore;
1545 if (HAS_PCH_NOP(dev_priv))
1548 if (HAS_PCH_IBX(dev_priv))
1550 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
1558 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
1560 lockdep_assert_held(&dev_priv->irq_lock);
1562 if (dev_priv->display.irq.display_irqs_enabled)
1565 dev_priv->display.irq.display_irqs_enabled = true;
1567 if (intel_irqs_enabled(dev_priv)) {
1568 vlv_display_irq_reset(dev_priv);
1569 vlv_display_irq_postinstall(dev_priv);
1573 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
1575 lockdep_assert_held(&dev_priv->irq_lock);
1577 if (!dev_priv->display.irq.display_irqs_enabled)
1580 dev_priv->display.irq.display_irqs_enabled = false;
1582 if (intel_irqs_enabled(dev_priv))
1583 vlv_display_irq_reset(dev_priv);
1630 void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
1632 struct intel_uncore *uncore = &dev_priv->uncore;
1634 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
1637 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
1644 if (!HAS_DISPLAY(dev_priv))
1647 if (DISPLAY_VER(dev_priv) >= 14)
1648 mtp_irq_postinstall(dev_priv);
1649 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
1650 icp_irq_postinstall(dev_priv);
1651 else if (HAS_PCH_SPLIT(dev_priv))
1652 ibx_irq_postinstall(dev_priv);
1654 if (DISPLAY_VER(dev_priv) < 11)
1657 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1660 if (DISPLAY_VER(dev_priv) >= 14) {
1663 } else if (DISPLAY_VER(dev_priv) >= 11) {
1666 if (intel_bios_is_dsi_present(dev_priv, &port))
1672 gen8_de_pipe_underrun_mask(dev_priv) |
1673 gen8_de_pipe_flip_done_mask(dev_priv);
1676 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1678 else if (IS_BROADWELL(dev_priv))
1681 if (DISPLAY_VER(dev_priv) >= 12) {
1684 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
1688 if (!intel_display_power_is_enabled(dev_priv, domain))
1697 for_each_pipe(dev_priv, pipe) {
1698 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked;
1700 if (intel_display_power_is_enabled(dev_priv,
1703 dev_priv->display.irq.de_irq_mask[pipe],
1710 if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
1734 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
1736 struct intel_uncore *uncore = &dev_priv->uncore;
1742 void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
1744 if (!HAS_DISPLAY(dev_priv))
1747 gen8_de_irq_postinstall(dev_priv);
1749 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,