i915/display/intel_display_irq.c

59 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits)
61 	ilk_update_display_irq(i915, bits, bits);
64 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits)
66 	ilk_update_display_irq(i915, bits, 0);
132 void bdw_enable_pipe_irq(struct drm_i915_private *i915,
135 	bdw_update_pipe_irq(i915, pipe, bits, bits);
138 void bdw_disable_pipe_irq(struct drm_i915_private *i915,
141 	bdw_update_pipe_irq(i915, pipe, bits, 0);
170 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits)
172 	ibx_display_interrupt_update(i915, bits, bits);
175 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
177 	ibx_display_interrupt_update(i915, bits, 0);
270 static bool i915_has_asle(struct drm_i915_private *i915)
272 	if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915))
275 	return intel_opregion_asle_present(i915);
280  * @dev_priv: i915 device private
340 static void flip_done_handler(struct drm_i915_private *i915,
343 	struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
345 	spin_lock(&i915->drm.event_lock);
352 	spin_unlock(&i915->drm.event_lock);
956 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
958 	if (DISPLAY_VER(i915) >= 9)
975 static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir)
980 	*pch_iir = intel_de_read(i915, SDEIIR);
990 		drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
992 		pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
993 		*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
994 		intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir);
997 	intel_de_write(i915, SDEIIR, *pch_iir);
1000 		intel_de_write(i915, PICAINTERRUPT_IER, pica_ier);
1150 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
1152 	void __iomem * const regs = intel_uncore_regs(&i915->uncore);
1165 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
1168 		intel_opregion_asle_intr(i915);
1171 void gen11_display_irq_handler(struct drm_i915_private *i915)
1173 	void __iomem * const regs = intel_uncore_regs(&i915->uncore);
1176 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
1182 	gen8_de_irq_handler(i915, disp_ctl);
1186 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
1207 	struct drm_i915_private *i915 = to_i915(crtc->dev);
1215 	if (i915->display.irq.vblank_enabled++ == 0)
1216 		intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1319 	struct drm_i915_private *i915 = to_i915(crtc->dev);
1323 	if (--i915->display.irq.vblank_enabled == 0)
1324 		intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
1586 void ilk_de_irq_postinstall(struct drm_i915_private *i915)
1588 	struct intel_uncore *uncore = &i915->uncore;
1591 	if (DISPLAY_VER(i915) >= 7) {
1611 	if (IS_HASWELL(i915)) {
1616 	if (IS_IRONLAKE_M(i915))
1619 	i915->irq_mask = ~display_mask;
1621 	ibx_irq_postinstall(i915);
1623 	GEN3_IRQ_INIT(uncore, DE, i915->irq_mask,
1627 static void mtp_irq_postinstall(struct drm_i915_private *i915);
1628 static void icp_irq_postinstall(struct drm_i915_private *i915);
1720 static void mtp_irq_postinstall(struct drm_i915_private *i915)
1722 	struct intel_uncore *uncore = &i915->uncore;
1753 void dg1_de_irq_postinstall(struct drm_i915_private *i915)
1755 	if (!HAS_DISPLAY(i915))
1758 	gen8_de_irq_postinstall(i915);
1759 	intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,
1763 void intel_display_irq_init(struct drm_i915_private *i915)
1765 	i915->drm.vblank_disable_immediate = true;
1774 	i915->display.irq.display_irqs_enabled = true;
1775 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1776 		i915->display.irq.display_irqs_enabled = false;
1778 	intel_hotplug_irq_init(i915);