i915/display/intel_display_device.c

859 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
861 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
877 		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
885 		drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
898 	drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
904 probe_display(struct drm_i915_private *i915)
906 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
910 		drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
919 	drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n",
925 void intel_display_device_probe(struct drm_i915_private *i915)
931 	i915->display.drm = &i915->drm;
933 	if (HAS_GMD_ID(i915))
934 		info = probe_gmdid_display(i915, &ver, &rel, &step);
936 		info = probe_display(i915);
938 	DISPLAY_INFO(i915) = info;
940 	memcpy(DISPLAY_RUNTIME_INFO(i915),
941 	       &DISPLAY_INFO(i915)->__runtime_defaults,
942 	       sizeof(*DISPLAY_RUNTIME_INFO(i915)));
944 	if (HAS_GMD_ID(i915)) {
945 		DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
946 		DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
947 		DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
950 	intel_display_params_copy(&i915->display.params);
953 void intel_display_device_remove(struct drm_i915_private *i915)
955 	intel_display_params_free(&i915->display.params);
958 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915)
960 	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
968 	if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915))
971 	if (IS_ICL_WITH_PORT_F(i915))
975 	if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
976 		for_each_pipe(i915, pipe)
978 	else if (DISPLAY_VER(i915) >= 11) {
979 		for_each_pipe(i915, pipe)
981 	} else if (DISPLAY_VER(i915) >= 9) {
987 	if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
988 		for_each_pipe(i915, pipe)
990 	else if (DISPLAY_VER(i915) >= 11)
991 		for_each_pipe(i915, pipe)
993 	else if (DISPLAY_VER(i915) == 10)
994 		for_each_pipe(i915, pipe)
996 	else if (IS_BROXTON(i915)) {
1009 	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1010 		for_each_pipe(i915, pipe)
1012 	} else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
1013 		for_each_pipe(i915, pipe)
1017 	if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
1018 	    !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
1019 		drm_info(&i915->drm, "Display not present, disabling\n");
1023 	if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
1024 		u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
1025 		u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
1038 		    (HAS_PCH_CPT(i915) &&
1040 			drm_info(&i915->drm,
1044 			drm_info(&i915->drm, "PipeC fused off\n");
1048 	} else if (DISPLAY_VER(i915) >= 9) {
1049 		u32 dfsm = intel_de_read(i915, SKL_DFSM);
1067 		if (DISPLAY_VER(i915) >= 12 &&
1083 		if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1086 		if (IS_DISPLAY_VER(i915, 10, 12) &&
1091 	if (DISPLAY_VER(i915) >= 20) {
1092 		u32 cap = intel_de_read(i915, XE2LPD_DE_CAP);
1100 			for_each_pipe(i915, pipe)
1112 void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
1114 	if (HAS_DISPLAY(i915))
1115 		__intel_display_device_info_runtime_init(i915);
1118 	if (!HAS_DISPLAY(i915)) {
1119 		i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1120 		i915->display.info.__device_info = &no_display;
1124 	if (!i915->display.params.nuclear_pageflip &&
1125 	    DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
1126 		i915->drm.driver_features &= ~DRIVER_ATOMIC;
1159 bool intel_display_device_enabled(struct drm_i915_private *i915)
1162 	drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915));
1164 	return !i915->display.params.disable_display &&
1165 		!intel_opregion_headless_sku(i915);