Lines Matching refs:dev_priv
134 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 val = vlv_cck_read(dev_priv, reg);
154 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
161 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
166 vlv_cck_get(dev_priv);
168 if (dev_priv->hpll_freq == 0)
169 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
171 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
173 vlv_cck_put(dev_priv);
178 void intel_update_czclk(struct drm_i915_private *dev_priv)
180 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
187 dev_priv->czclk_freq);
198 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
200 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
207 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
217 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
220 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
301 if (DISPLAY_VER(dev_priv) >= 4) {
305 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
307 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
313 void assert_transcoder(struct drm_i915_private *dev_priv,
321 if (IS_I830(dev_priv))
325 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
327 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
330 intel_display_power_put(dev_priv, power_domain, wakeref);
335 I915_STATE_WARN(dev_priv, cur_state != state,
360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
363 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
367 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
393 if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
394 drm_WARN(&dev_priv->drm, 1,
397 intel_de_read(dev_priv, dpll_reg) & port_mask,
404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
409 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
418 if (HAS_GMCH(dev_priv)) {
420 assert_dsi_pll_enabled(dev_priv);
422 assert_pll_enabled(dev_priv, pipe);
426 assert_fdi_rx_pll_enabled(dev_priv,
428 assert_fdi_tx_pll_enabled(dev_priv,
435 if (DISPLAY_VER(dev_priv) == 13)
436 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
439 if (DISPLAY_VER(dev_priv) >= 14) {
443 if (DISPLAY_VER(dev_priv) == 14)
446 intel_de_rmw(dev_priv,
447 hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
451 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
454 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
459 if (DISPLAY_VER(dev_priv) >= 13 &&
466 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
468 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
489 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
497 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
509 if (!IS_I830(dev_priv))
513 if (DISPLAY_VER(dev_priv) >= 13 &&
517 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
519 if (DISPLAY_VER(dev_priv) >= 12)
520 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
566 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
568 return DISPLAY_VER(dev_priv) < 4 ||
604 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
610 if (!HAS_DISPLAY(dev_priv))
618 crtc = intel_first_crtc(dev_priv);
644 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
655 drm_for_each_plane_mask(plane, &dev_priv->drm,
665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
671 drm_dbg_kms(&dev_priv->drm,
699 if (HAS_GMCH(dev_priv) &&
700 intel_set_memory_cxsr(dev_priv, false))
707 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
708 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
728 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
732 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
752 if (IS_DG2(dev_priv))
754 else if (DISPLAY_VER(dev_priv) >= 13)
758 if (IS_DG2(dev_priv))
761 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
764 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
769 drm_for_each_crtc(crtc, &dev_priv->drm) {
824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
839 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
840 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
843 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
845 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
847 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
863 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
869 if (DISPLAY_VER(dev_priv) == 9)
877 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
880 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
888 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
893 DISPLAY_VER(dev_priv) == 11)
1055 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1064 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1067 intel_update_watermarks(dev_priv);
1073 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1077 skl_wa_827(dev_priv, pipe, false);
1081 icl_wa_scalerclkgating(dev_priv, pipe, false);
1085 icl_wa_cursorclkgating(dev_priv, pipe, false);
1163 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1190 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1195 skl_wa_827(dev_priv, pipe, true);
1200 icl_wa_scalerclkgating(dev_priv, pipe, true);
1205 icl_wa_cursorclkgating(dev_priv, pipe, true);
1216 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1217 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1228 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1252 intel_update_watermarks(dev_priv);
1263 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1264 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1277 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1299 intel_frontbuffer_flip(dev_priv, fb_bits);
1513 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1516 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1529 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1530 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1543 assert_fdi_tx_disabled(dev_priv, pipe);
1544 assert_fdi_rx_disabled(dev_priv, pipe);
1569 if (HAS_PCH_CPT(dev_priv))
1582 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1583 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1608 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1640 if (HAS_VRR(dev_priv))
1644 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1661 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1664 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1666 intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
1670 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1681 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1688 if (DISPLAY_VER(dev_priv) >= 13)
1693 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1700 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1710 if (DISPLAY_VER(dev_priv) >= 9)
1723 if (DISPLAY_VER(dev_priv) < 9)
1728 if (DISPLAY_VER(dev_priv) >= 11)
1736 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1752 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1754 intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1773 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1774 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1775 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1791 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1792 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1810 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1811 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1858 drm_WARN_ON(&dev_priv->drm,
1859 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1860 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1862 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1864 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1868 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1872 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1876 else if (IS_ALDERLAKE_S(dev_priv))
1878 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1880 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1882 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1894 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1901 if (IS_DG2(dev_priv))
1904 if (DISPLAY_VER(dev_priv) >= 13)
1906 else if (IS_TIGERLAKE(dev_priv))
1908 else if (IS_ICELAKE(dev_priv))
1915 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1921 return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
1943 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1945 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1948 if (DISPLAY_VER(dev_priv) >= 12)
2004 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2020 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2027 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2041 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2057 intel_display_power_get_in_set(dev_priv,
2092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2095 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2102 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
2104 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2105 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2106 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2111 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2115 if (IS_CHERRYVIEW(dev_priv))
2143 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2146 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2155 if (DISPLAY_VER(dev_priv) != 2)
2156 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2171 intel_update_watermarks(dev_priv);
2179 if (DISPLAY_VER(dev_priv) == 2)
2186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2191 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2193 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2194 intel_de_read(dev_priv, PFIT_CONTROL));
2195 intel_de_write(dev_priv, PFIT_CONTROL, 0);
2203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2210 if (DISPLAY_VER(dev_priv) == 2)
2224 if (IS_CHERRYVIEW(dev_priv))
2225 chv_disable_pll(dev_priv, pipe);
2226 else if (IS_VALLEYVIEW(dev_priv))
2227 vlv_disable_pll(dev_priv, pipe);
2234 if (DISPLAY_VER(dev_priv) != 2)
2235 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2237 if (!dev_priv->display.funcs.wm->initial_watermarks)
2238 intel_update_watermarks(dev_priv);
2241 if (IS_I830(dev_priv))
2242 i830_enable_pipe(dev_priv, pipe);
2255 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2258 return DISPLAY_VER(dev_priv) < 4 &&
2259 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2306 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2308 if (HAS_GMCH(dev_priv))
2574 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2582 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2583 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2587 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2588 drm_dbg_kms(&dev_priv->drm,
2591 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2592 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2619 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2622 if (IS_HASWELL(dev_priv))
2625 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2635 if (DISPLAY_VER(dev_priv) >= 5)
2636 intel_set_m_n(dev_priv, m_n,
2640 intel_set_m_n(dev_priv, m_n,
2649 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2651 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2654 intel_set_m_n(dev_priv, m_n,
2662 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2694 if (DISPLAY_VER(dev_priv) >= 13) {
2695 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2705 if (DISPLAY_VER(dev_priv) >= 4)
2706 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2709 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2712 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2715 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2719 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2722 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2725 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2733 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2735 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2753 drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2759 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2766 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2774 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2782 intel_de_write(dev_priv, PIPESRC(pipe),
2788 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2791 if (DISPLAY_VER(dev_priv) == 2)
2794 if (DISPLAY_VER(dev_priv) >= 9 ||
2795 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2796 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2798 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2805 struct drm_i915_private *dev_priv = to_i915(dev);
2810 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2815 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2820 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2824 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2830 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2834 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2844 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2847 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2871 struct drm_i915_private *dev_priv = to_i915(dev);
2874 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2886 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2895 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2902 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2903 IS_CHERRYVIEW(dev_priv)) {
2927 if (DISPLAY_VER(dev_priv) < 4 ||
2936 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2947 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2948 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2951 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2953 if (IS_I830(dev_priv))
2956 return DISPLAY_VER(dev_priv) >= 4 ||
2957 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2963 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2967 if (!i9xx_has_pfit(dev_priv))
2970 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2975 if (DISPLAY_VER(dev_priv) >= 4)
2985 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2994 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2998 drm_WARN_ON(&dev_priv->drm,
3012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3019 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3030 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3034 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3035 IS_CHERRYVIEW(dev_priv)) {
3052 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3060 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3066 if (DISPLAY_VER(dev_priv) < 4)
3076 if (DISPLAY_VER(dev_priv) >= 4) {
3081 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3082 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3094 if (IS_CHERRYVIEW(dev_priv))
3096 else if (IS_VALLEYVIEW(dev_priv))
3112 intel_display_power_put(dev_priv, power_domain, wakeref);
3120 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3162 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3177 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3178 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195 if (IS_HASWELL(dev_priv) && crtc_state->dither)
3203 if (IS_HASWELL(dev_priv) &&
3207 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3208 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3229 if (DISPLAY_VER(dev_priv) >= 13)
3248 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3251 if (DISPLAY_VER(dev_priv) >= 12)
3255 if (IS_BROADWELL(dev_priv))
3258 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3266 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3286 if (DISPLAY_VER(dev_priv) >= 13)
3322 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3325 if (DISPLAY_VER(dev_priv) >= 5)
3326 intel_get_m_n(dev_priv, m_n,
3330 intel_get_m_n(dev_priv, m_n,
3339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3341 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3344 intel_get_m_n(dev_priv, m_n,
3352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3356 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3360 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3367 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3368 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3381 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3388 struct drm_i915_private *dev_priv = to_i915(dev);
3395 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3403 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3459 intel_display_power_put(dev_priv, power_domain, wakeref);
3478 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3487 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3488 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3493 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3501 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3502 bigjoiner_pipes(dev_priv)) {
3508 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3509 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3520 if (DISPLAY_VER(dev_priv) < 13)
3524 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3525 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3535 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3584 struct drm_i915_private *dev_priv = to_i915(dev);
3585 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3594 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3602 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3603 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3635 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3639 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3643 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3688 struct drm_i915_private *dev_priv = to_i915(dev);
3696 assert_enabled_transcoders(dev_priv, enabled_transcoders);
3705 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3709 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3710 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3716 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3726 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3737 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3748 if (!bxt_dsi_pll_is_enabled(dev_priv))
3787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3791 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3799 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3801 drm_WARN_ON(&dev_priv->drm, active);
3812 DISPLAY_VER(dev_priv) >= 11)
3815 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3820 if (IS_HASWELL(dev_priv)) {
3821 u32 tmp = intel_de_read(dev_priv,
3837 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3839 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3843 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3845 if (DISPLAY_VER(dev_priv) >= 9)
3856 intel_de_read(dev_priv,
3863 tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
3872 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3951 crtc = intel_crtc_for_pipe(dev_priv, pipe);
4036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4042 if (DISPLAY_VER(dev_priv) < 11)
4075 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4076 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4090 drm_dbg_kms(&dev_priv->drm,
4108 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4121 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4195 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4196 skl_watermark_ipc_enabled(dev_priv))
4205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4210 if (DISPLAY_VER(dev_priv) >= 9)
4231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4236 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4262 drm_dbg_kms(&dev_priv->drm,
4274 drm_dbg_kms(&dev_priv->drm,
4279 if (DISPLAY_VER(dev_priv) >= 9) {
4287 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4292 if (HAS_IPS(dev_priv)) {
4298 if (DISPLAY_VER(dev_priv) >= 9 ||
4299 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4366 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4367 IS_CHERRYVIEW(dev_priv)))
4369 else if (DISPLAY_VER(dev_priv) >= 5)
4581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4606 if (IS_G4X(dev_priv) ||
4607 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5008 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5014 p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);
5016 p = drm_err_printer(&dev_priv->drm, NULL);
5097 if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
5164 pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5228 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5262 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5263 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5279 if (DISPLAY_VER(dev_priv) < 4)
5299 if (IS_CHERRYVIEW(dev_priv))
5331 if (dev_priv->display.dpll.mgr)
5335 if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
5341 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5541 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5544 for_each_intel_crtc(&dev_priv->drm, crtc) {
5650 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5654 if (IS_HASWELL(dev_priv))
5694 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5697 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5724 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5727 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5728 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5729 IS_IVYBRIDGE(dev_priv);
5777 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5795 drm_dbg_atomic(&dev_priv->drm,
5815 if (!active_planes_affects_min_cdclk(dev_priv))
6409 struct drm_i915_private *dev_priv = to_i915(dev);
6416 if (!intel_display_driver_check_access(dev_priv))
6457 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6528 drm_dbg_kms(&dev_priv->drm,
6584 drm_WARN_ON(&dev_priv->drm,
6635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6637 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6638 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6644 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6665 if (DISPLAY_VER(dev_priv) >= 9) {
6668 } else if (HAS_PCH_SPLIT(dev_priv)) {
6683 if (DISPLAY_VER(dev_priv) >= 9 ||
6684 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6698 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6713 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6728 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6739 if (DISPLAY_VER(dev_priv) >= 9 &&
6750 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6758 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
6767 dev_priv->display.funcs.display->crtc_enable(state, crtc);
6861 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6870 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
6874 dev_priv->display.funcs.display->crtc_disable(state, crtc);
6876 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
6983 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7125 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7134 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7135 drm_WARN_ON(&dev_priv->drm, update_pipes);
7221 struct drm_i915_private *dev_priv = to_i915(dev);
7261 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7323 dev_priv->display.funcs.display->commit_modeset_enables(state);
7365 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7366 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7400 intel_check_cpu_fifo_underruns(dev_priv);
7401 intel_check_pch_fifo_underruns(dev_priv);
7419 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7425 intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7426 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7497 struct drm_i915_private *dev_priv = to_i915(dev);
7500 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7519 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7532 drm_dbg_atomic(&dev_priv->drm,
7534 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7551 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7559 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7561 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7564 flush_workqueue(dev_priv->display.wq.modeset);
7627 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7629 if (!IS_MOBILE(dev_priv))
7632 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7635 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7641 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7643 if (DISPLAY_VER(dev_priv) >= 9)
7646 if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7649 if (HAS_PCH_LPT_H(dev_priv) &&
7650 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7654 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7657 if (!dev_priv->display.vbt.int_crt_support)
7669 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7674 intel_pps_unlock_regs_wa(dev_priv);
7676 if (!HAS_DISPLAY(dev_priv))
7679 if (HAS_DDI(dev_priv)) {
7680 if (intel_ddi_crt_present(dev_priv))
7681 intel_crt_init(dev_priv);
7683 intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
7685 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
7686 vlv_dsi_init(dev_priv);
7687 } else if (HAS_PCH_SPLIT(dev_priv)) {
7695 intel_lvds_init(dev_priv);
7696 intel_crt_init(dev_priv);
7698 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7700 if (ilk_has_edp_a(dev_priv))
7701 g4x_dp_init(dev_priv, DP_A, PORT_A);
7703 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7705 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7707 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7708 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7709 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7712 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7713 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7715 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7716 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7718 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7719 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7721 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7722 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7723 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7726 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7727 intel_crt_init(dev_priv);
7744 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7745 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7746 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7747 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7748 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7749 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7751 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7752 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7753 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7754 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7755 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7756 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7758 if (IS_CHERRYVIEW(dev_priv)) {
7763 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7764 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7765 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7766 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7767 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7770 vlv_dsi_init(dev_priv);
7771 } else if (IS_PINEVIEW(dev_priv)) {
7772 intel_lvds_init(dev_priv);
7773 intel_crt_init(dev_priv);
7774 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7777 if (IS_MOBILE(dev_priv))
7778 intel_lvds_init(dev_priv);
7780 intel_crt_init(dev_priv);
7782 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7783 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7784 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7785 if (!found && IS_G4X(dev_priv)) {
7786 drm_dbg_kms(&dev_priv->drm,
7788 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7791 if (!found && IS_G4X(dev_priv))
7792 g4x_dp_init(dev_priv, DP_B, PORT_B);
7797 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7798 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7799 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7802 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7804 if (IS_G4X(dev_priv)) {
7805 drm_dbg_kms(&dev_priv->drm,
7807 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7809 if (IS_G4X(dev_priv))
7810 g4x_dp_init(dev_priv, DP_C, PORT_C);
7813 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7814 g4x_dp_init(dev_priv, DP_D, PORT_D);
7816 if (SUPPORTS_TV(dev_priv))
7817 intel_tv_init(dev_priv);
7818 } else if (DISPLAY_VER(dev_priv) == 2) {
7819 if (IS_I85X(dev_priv))
7820 intel_lvds_init(dev_priv);
7822 intel_crt_init(dev_priv);
7823 intel_dvo_init(dev_priv);
7826 for_each_intel_encoder(&dev_priv->drm, encoder) {
7833 intel_init_pch_refclk(dev_priv);
7835 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7852 struct drm_i915_private *dev_priv = to_i915(dev);
7889 if (mode->clock > max_dotclock(dev_priv))
7893 if (DISPLAY_VER(dev_priv) >= 11) {
7898 } else if (DISPLAY_VER(dev_priv) >= 9 ||
7899 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7904 } else if (DISPLAY_VER(dev_priv) >= 3) {
7931 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
7938 if (DISPLAY_VER(dev_priv) >= 5) {
7957 if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
7965 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7975 if (DISPLAY_VER(dev_priv) < 9)
7983 if (DISPLAY_VER(dev_priv) >= 11) {
8047 * @dev_priv: device private
8049 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8051 if (DISPLAY_VER(dev_priv) >= 9) {
8052 dev_priv->display.funcs.display = &skl_display_funcs;
8053 } else if (HAS_DDI(dev_priv)) {
8054 dev_priv->display.funcs.display = &ddi_display_funcs;
8055 } else if (HAS_PCH_SPLIT(dev_priv)) {
8056 dev_priv->display.funcs.display = &pch_split_display_funcs;
8057 } else if (IS_CHERRYVIEW(dev_priv) ||
8058 IS_VALLEYVIEW(dev_priv)) {
8059 dev_priv->display.funcs.display = &vlv_display_funcs;
8061 dev_priv->display.funcs.display = &i9xx_display_funcs;
8136 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8138 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8151 drm_WARN_ON(&dev_priv->drm,
8154 drm_dbg_kms(&dev_priv->drm,
8166 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8168 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8170 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8172 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8174 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8176 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8178 intel_de_write(dev_priv, PIPESRC(pipe),
8181 intel_de_write(dev_priv, FP0(pipe), fp);
8182 intel_de_write(dev_priv, FP1(pipe), fp);
8189 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8190 intel_de_write(dev_priv, DPLL(pipe), dpll);
8193 intel_de_posting_read(dev_priv, DPLL(pipe));
8201 intel_de_write(dev_priv, DPLL(pipe), dpll);
8205 intel_de_write(dev_priv, DPLL(pipe), dpll);
8206 intel_de_posting_read(dev_priv, DPLL(pipe));
8210 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8211 intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8216 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8218 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8220 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8223 drm_WARN_ON(&dev_priv->drm,
8224 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8225 drm_WARN_ON(&dev_priv->drm,
8226 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8227 drm_WARN_ON(&dev_priv->drm,
8228 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8229 drm_WARN_ON(&dev_priv->drm,
8230 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8231 drm_WARN_ON(&dev_priv->drm,
8232 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8234 intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8235 intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8239 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8240 intel_de_posting_read(dev_priv, DPLL(pipe));