i915/display/intel_display.c

320 	/* we keep both pipes enabled on 830 */
453 		/* we keep both pipes enabled on 830 */
2891 	 * - We keep both pipes enabled on 830
2904 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
3466 	u8 pipes;
3469 		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3471 		pipes = BIT(PIPE_B) | BIT(PIPE_C);
3473 		pipes = 0;
3475 	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3534 	/* Bigjoiner pipes should always be consecutive master and slave */
3536 		 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
5480  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5483  * @mask: mask of pipes to modeset
5485  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5528  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5532  * Add all pipes to @state and force a full modeset on the active ones due to
5572  * set sequence documentation. When going from no pipes or single pipe to
5573  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5872 				     u8 pipes)
5880 		    pipes & BIT(crtc->pipe) &&
5907 			    "(need 0x%x as pipes, only 0x%x possible)\n",
6478 	 * pipes and transcoders.
6903 		 * Needs to be done even for pipes
7006 	 * Whenever the number of active pipes changes, we need to make sure we
7007 	 * update the pipes in the right order so that their ddb allocations
7011 	 * So first lets enable all pipes that do not need a fullmodeset as
7064 	 * Enable all pipes that needs a modeset and do not depends on other
7065 	 * pipes
7086 	 * Then we enable all remaining pipes that depend on other
7087 	 * pipes: MST slaves and port sync masters, big joiner master
7104 	 * Finally we do the plane updates/etc. for all pipes that got enabled.
7298 	/* Complete the events for pipes that have now been disabled */
7302 		/* Complete events for now disable pipes here. */