i915/display/intel_ddi.c

1115 	int n_entries, ln;
1141 	for (ln = 0; ln < 4; ln++) {
1142 		int level = intel_ddi_level(encoder, crtc_state, ln);
1144 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1153 	for (ln = 0; ln < 4; ln++) {
1154 		int level = intel_ddi_level(encoder, crtc_state, ln);
1156 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1164 	for (ln = 0; ln < 4; ln++) {
1165 		int level = intel_ddi_level(encoder, crtc_state, ln);
1167 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1179 	int ln;
1200 	for (ln = 0; ln < 4; ln++) {
1201 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1203 			     icl_combo_phy_loadgen_select(crtc_state, ln));
1230 	int n_entries, ln;
1239 	for (ln = 0; ln < 2; ln++) {
1240 		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1242 		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1247 	for (ln = 0; ln < 2; ln++) {
1250 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1252 		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1256 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1258 		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1264 	for (ln = 0; ln < 2; ln++) {
1267 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1269 		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1276 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1278 		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1293 	for (ln = 0; ln < 2; ln++) {
1294 		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1300 	for (ln = 0; ln < 2; ln++) {
1301 		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1308 		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1317 	for (ln = 0; ln < 2; ln++) {
1318 		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1320 		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1331 	int n_entries, ln;
1340 	for (ln = 0; ln < 2; ln++) {
1343 		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1345 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1347 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1355 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1357 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1365 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1372 				if (ln == 0) {
1384 			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
3533 	int ln;
3535 	for (ln = 0; ln < 2; ln++)
3536 		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);