i915/display/intel_ddi.c

1117 	int n_entries, ln;
1143 	for (ln = 0; ln < 4; ln++) {
1144 		int level = intel_ddi_level(encoder, crtc_state, ln);
1146 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1155 	for (ln = 0; ln < 4; ln++) {
1156 		int level = intel_ddi_level(encoder, crtc_state, ln);
1158 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1166 	for (ln = 0; ln < 4; ln++) {
1167 		int level = intel_ddi_level(encoder, crtc_state, ln);
1169 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1181 	int ln;
1202 	for (ln = 0; ln < 4; ln++) {
1203 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1205 			     icl_combo_phy_loadgen_select(crtc_state, ln));
1232 	int n_entries, ln;
1241 	for (ln = 0; ln < 2; ln++) {
1242 		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1244 		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1249 	for (ln = 0; ln < 2; ln++) {
1252 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1254 		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1258 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1260 		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1266 	for (ln = 0; ln < 2; ln++) {
1269 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1271 		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1278 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1280 		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1295 	for (ln = 0; ln < 2; ln++) {
1296 		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1302 	for (ln = 0; ln < 2; ln++) {
1303 		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1310 		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1319 	for (ln = 0; ln < 2; ln++) {
1320 		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1322 		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1333 	int n_entries, ln;
1342 	for (ln = 0; ln < 2; ln++) {
1345 		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1347 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1349 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1357 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1359 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1367 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1374 				if (ln == 0) {
1386 			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
3524 	int ln;
3526 	for (ln = 0; ln < 2; ln++)
3527 		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);