i915/display/intel_cx0_phy_regs.h

34 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
38 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
39 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane)				\
41 	 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) :		\
42 	 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
54 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
58 										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
59 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane)			\
61 	 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) :	\
62 	 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
119 #define   XELPDP_LANE_PIPE_RESET(lane)			_PICK(lane, REG_BIT(31), REG_BIT(30))
120 #define   XELPDP_LANE_PHY_CURRENT_STATUS(lane)		_PICK(lane, REG_BIT(29), REG_BIT(28))
121 #define   XELPDP_LANE_POWERDOWN_UPDATE(lane)		_PICK(lane, REG_BIT(25), REG_BIT(24))
126 #define   XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val)	_PICK(lane, \
156 #define _XELPDP_PORT_MSGBUS_TIMER(port, lane)		_MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
160 										 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
161 #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane)				\
163 	 _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) :		\
164 	 _XELPDP_PORT_MSGBUS_TIMER(port, lane))
182 #define   XELPDP_LANE_PCLK_PLL_REQUEST(lane)		REG_BIT(31 - ((lane) * 4))
183 #define   XELPDP_LANE_PCLK_PLL_ACK(lane)		REG_BIT(30 - ((lane) * 4))
184 #define   XELPDP_LANE_PCLK_REFCLK_REQUEST(lane)		REG_BIT(29 - ((lane) * 4))
185 #define   XELPDP_LANE_PCLK_REFCLK_ACK(lane)		REG_BIT(28 - ((lane) * 4))
232 #define PHY_CX0_VDROVRD_CTL(lane, tx, control)				\
234 					 ((lane) ^ (tx)) * 0x10 + (control))