i915/display/intel_cx0_phy.c

28 #define INTEL_CX0_LANE0		BIT(0)
30 #define INTEL_CX0_BOTH_LANES	(INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
64 		? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
469 		u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
1875 	u8 lane = INTEL_CX0_LANE0;
1919 		intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),
1923 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);
1924 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);
1926 	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
2168 	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
2173 			pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2176 			pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2183 			pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2186 			pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2194 				pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2197 				pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2204 				pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2207 				pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
2340 	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
2349 	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);
2358 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
2366 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
2368 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
2374 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
2376 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
2383 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2387 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2394 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2398 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2599 	u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
2675 		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
2723 					  INTEL_CX0_LANE0;