i915/display/intel_cursor.c

37 	struct drm_i915_private *dev_priv =
41 	if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
94 	struct drm_i915_private *dev_priv =
116 		drm_dbg_kms(&dev_priv->drm,
129 	if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
274 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
296 		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
297 		intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
298 		intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
299 		intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
300 		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
306 		intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
319 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
325 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
329 	ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
333 	intel_display_power_put(dev_priv, power_domain, wakeref);
349 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
352 	if (DISPLAY_VER(dev_priv) >= 11)
361 	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
370 	struct drm_i915_private *dev_priv =
374 	if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
396 	if (DISPLAY_VER(dev_priv) == 13)
404 	struct drm_i915_private *dev_priv =
428 	if (HAS_CUR_FBC(dev_priv) &&
444 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
459 		drm_dbg(&dev_priv->drm,
466 	drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
471 		drm_dbg_kms(&dev_priv->drm,
488 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
490 		drm_dbg_kms(&dev_priv->drm,
503 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
509 	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
516 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
524 	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
526 	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
534 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
544 			intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
547 		intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
563 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
601 	if (DISPLAY_VER(dev_priv) >= 9)
613 		if (HAS_CUR_FBC(dev_priv))
614 			intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
616 		intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
617 		intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
618 		intel_de_write_fw(dev_priv, CURBASE(pipe), base);
624 		intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
625 		intel_de_write_fw(dev_priv, CURBASE(pipe), base);
638 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
650 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
654 	val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
658 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
663 	intel_display_power_put(dev_priv, power_domain, wakeref);
869 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
885 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
902 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
905 	modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
907 	ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
920 	if (DISPLAY_VER(dev_priv) >= 4)
928 	zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
931 	if (DISPLAY_VER(dev_priv) >= 12)