i915/display/intel_crt.c

104 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
113 	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
123 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
126 	tmp = intel_de_read(dev_priv, crt->adpa_reg);
172 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
213 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
474 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
480 	if (crt->force_hotplug_required) {
484 		crt->force_hotplug_required = false;
486 		save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
494 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
497 					    crt->adpa_reg,
504 			intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
505 			intel_de_posting_read(dev_priv, crt->adpa_reg);
510 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
524 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
543 	reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
545 	save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
551 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
553 	if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
557 		intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
561 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
571 		intel_hpd_enable(dev_priv, crt->base.hpd_pin);
662 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
663 	struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
694 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
696 	struct drm_device *dev = crt->base.base.dev;
834 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
835 	struct intel_encoder *intel_encoder = &crt->base;
908 			status = intel_crt_load_detect(crt,
927 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
928 	struct intel_encoder *intel_encoder = &crt->base;
956 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
961 		adpa = intel_de_read(dev_priv, crt->adpa_reg);
964 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
965 		intel_de_posting_read(dev_priv, crt->adpa_reg);
967 		drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
968 		crt->force_hotplug_required = true;
1000 	struct intel_crt *crt;
1030 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1031 	if (!crt)
1036 		kfree(crt);
1043 	crt->connector = intel_connector;
1049 	drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1052 	intel_connector_attach_encoder(intel_connector, &crt->base);
1054 	crt->base.type = INTEL_OUTPUT_ANALOG;
1055 	crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1057 		crt->base.pipe_mask = BIT(PIPE_A);
1059 		crt->base.pipe_mask = ~0;
1064 	crt->adpa_reg = adpa_reg;
1066 	crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1070 		crt->base.hpd_pin = HPD_CRT;
1071 		crt->base.hotplug = intel_encoder_hotplug;
1081 		crt->base.port = PORT_E;
1082 		crt->base.get_config = hsw_crt_get_config;
1083 		crt->base.get_hw_state = intel_ddi_get_hw_state;
1084 		crt->base.compute_config = hsw_crt_compute_config;
1085 		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1086 		crt->base.pre_enable = hsw_pre_enable_crt;
1087 		crt->base.enable = hsw_enable_crt;
1088 		crt->base.disable = hsw_disable_crt;
1089 		crt->base.post_disable = hsw_post_disable_crt;
1090 		crt->base.enable_clock = hsw_ddi_enable_clock;
1091 		crt->base.disable_clock = hsw_ddi_disable_clock;
1092 		crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1094 		intel_ddi_buf_trans_init(&crt->base);
1097 			crt->base.compute_config = pch_crt_compute_config;
1098 			crt->base.disable = pch_disable_crt;
1099 			crt->base.post_disable = pch_post_disable_crt;
1101 			crt->base.compute_config = intel_crt_compute_config;
1102 			crt->base.disable = intel_disable_crt;
1104 		crt->base.port = PORT_NONE;
1105 		crt->base.get_config = intel_crt_get_config;
1106 		crt->base.get_hw_state = intel_crt_get_hw_state;
1107 		crt->base.enable = intel_enable_crt;
1126 	intel_crt_reset(&crt->base.base);