i915/display/intel_cdclk.c

50  * are two main clocks involved that aren't directly related to the actual
51  * pixel clock or any symbol/bit clock of the actual output port. These
549 		 * Specs are full of misinformation, but testing on actual
2506 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2507 				 &new_cdclk_state->actual) &&
2515 	change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2526 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2552 	voltage_level = new_cdclk_state->actual.voltage_level;
2554 	update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2563 		cdclk = new_cdclk_state->actual.cdclk;
2586 		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2607 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2608 				 &new_cdclk_state->actual))
2615 		cdclk_config = new_cdclk_state->actual;
2618 		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2619 			cdclk_config = new_cdclk_state->actual;
2622 			cdclk_config = old_cdclk_state->actual;
2626 		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2627 						 old_cdclk_state->actual.voltage_level);
2634 	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2659 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2660 				 &new_cdclk_state->actual))
2667 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2674 	intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,
2966 		cdclk_state->actual.cdclk = cdclk;
2967 		cdclk_state->actual.voltage_level =
2970 		cdclk_state->actual = cdclk_state->logical;
2993 		cdclk_state->actual.cdclk = cdclk;
2994 		cdclk_state->actual.voltage_level =
2997 		cdclk_state->actual = cdclk_state->logical;
3060 		cdclk_state->actual.vco = vco;
3061 		cdclk_state->actual.cdclk = cdclk;
3062 		cdclk_state->actual.voltage_level =
3065 		cdclk_state->actual = cdclk_state->logical;
3098 		cdclk_state->actual.vco = vco;
3099 		cdclk_state->actual.cdclk = cdclk;
3100 		cdclk_state->actual.voltage_level =
3103 		cdclk_state->actual = cdclk_state->logical;
3116 	 * the actual cdclk frequency.
3206 	cdclk_state->actual.joined_mbus = joined_mbus;
3232 	bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3233 						 &new_cdclk_state->actual);
3265 		 * if the actual hw needs to be poked.
3283 					&old_cdclk_state->actual,
3284 					&new_cdclk_state->actual)) {
3300 					     &old_cdclk_state->actual,
3301 					     &new_cdclk_state->actual)) {
3305 					&old_cdclk_state->actual,
3306 					&new_cdclk_state->actual)) {
3310 					 &old_cdclk_state->actual,
3311 					 &new_cdclk_state->actual)) {
3320 	} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3321 					     &new_cdclk_state->actual)) {
3333 	if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
3334 	    intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
3335 		int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
3343 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3345 		    new_cdclk_state->actual.cdclk);
3347 		    "New voltage level calculated to be logical %u, actual %u\n",
3349 		    new_cdclk_state->actual.voltage_level);
3532 	 * straps, not the actual FSB frequency. Some BIOSen
3534 	 * read out the actual FSB frequency but sadly we