i915/display/intel_bw.c

212 			      struct intel_qgv_info *qi,
218 	qi->num_points = dram_info->num_qgv_points;
219 	qi->num_psf_points = dram_info->num_psf_gv_points;
224 			qi->t_bl = 4;
225 			qi->max_numchannels = 2;
226 			qi->channel_width = 64;
227 			qi->deinterleave = 2;
230 			qi->t_bl = 8;
231 			qi->max_numchannels = 4;
232 			qi->channel_width = 32;
233 			qi->deinterleave = 2;
237 			qi->t_bl = 16;
238 			qi->max_numchannels = 8;
239 			qi->channel_width = 16;
240 			qi->deinterleave = 4;
249 			qi->t_bl = is_y_tile ? 8 : 4;
250 			qi->max_numchannels = 2;
251 			qi->channel_width = 64;
252 			qi->deinterleave = is_y_tile ? 1 : 2;
255 			qi->t_bl = is_y_tile ? 16 : 8;
256 			qi->max_numchannels = 4;
257 			qi->channel_width = 32;
258 			qi->deinterleave = is_y_tile ? 1 : 2;
262 				qi->t_bl = 8;
263 				qi->max_numchannels = 4;
264 				qi->channel_width = 32;
265 				qi->deinterleave = 2;
270 			qi->t_bl = 16;
271 			qi->max_numchannels = 8;
272 			qi->channel_width = 16;
273 			qi->deinterleave = is_y_tile ? 2 : 4;
276 			qi->t_bl = 16;
277 			qi->max_numchannels = 1;
281 		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
282 		qi->max_numchannels = 1;
286 			qi->num_points > ARRAY_SIZE(qi->points)))
287 		qi->num_points = ARRAY_SIZE(qi->points);
289 	for (i = 0; i < qi->num_points; i++) {
290 		struct intel_qgv_point *sp = &qi->points[i];
302 	if (qi->num_psf_points > 0) {
303 		ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
306 			qi->num_psf_points = 0;
309 		for (i = 0; i < qi->num_psf_points; i++)
312 				    i, qi->psf_points[i].clk);
328 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
333 	for (i = 0; i < qi->num_points; i++)
334 		dclk = max(dclk, qi->points[i].dclk);
388 	struct intel_qgv_info qi = {};
397 	ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
404 	dclk_max = icl_sagv_max_dclk(&qi);
407 	qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
414 		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
417 		bi->num_qgv_points = qi.num_points;
418 		bi->num_psf_gv_points = qi.num_psf_points;
420 		for (j = 0; j < qi.num_points; j++) {
421 			const struct intel_qgv_point *sp = &qi.points[j];
431 				   (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
447 	if (qi.num_points == 1)
457 	struct intel_qgv_info qi = {};
468 	ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
479 	qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
481 	if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
482 		qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
484 	if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
486 	if (qi.max_numchannels != 0)
487 		num_channels = min_t(u8, num_channels, qi.max_numchannels);
489 	dclk_max = icl_sagv_max_dclk(&qi);
491 	peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
499 	clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
507 		clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
519 		bi->num_qgv_points = qi.num_points;
520 		bi->num_psf_gv_points = qi.num_psf_points;
522 		for (j = 0; j < qi.num_points; j++) {
523 			const struct intel_qgv_point *sp = &qi.points[j];
533 				   (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
540 							  qi.channel_width, 8);
548 		for (j = 0; j < qi.num_psf_points; j++) {
549 			const struct intel_psf_gv_point *sp = &qi.psf_points[j];
564 	if (qi.num_points == 1)