i915/display/intel_bw.c

905 			       struct intel_bw_state *new_bw_state)
913 	ret = intel_atomic_lock_global_state(&new_bw_state->base);
922 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
923 		new_bw_state->qgv_point_peakbw = U16_MAX;
968 	new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
977 			       struct intel_bw_state *new_bw_state)
986 	ret = intel_atomic_lock_global_state(&new_bw_state->base);
1035 	if (!intel_can_enable_sagv(i915, new_bw_state)) {
1045 	new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915,
1052 	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1053 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1063 				     struct intel_bw_state *new_bw_state)
1065 	unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);
1067 			intel_bw_num_active_planes(i915, new_bw_state);
1073 					   new_bw_state);
1076 					   old_bw_state, new_bw_state);
1081 				   const struct intel_bw_state *new_bw_state)
1089 			&new_bw_state->dbuf_bw[pipe];
1098 		if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
1207 	struct intel_bw_state *new_bw_state = NULL;
1219 		new_bw_state = intel_atomic_get_bw_state(state);
1220 		if (IS_ERR(new_bw_state))
1221 			return PTR_ERR(new_bw_state);
1225 		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
1227 		new_bw_state->min_cdclk[crtc->pipe] =
1234 	if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
1235 		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
1241 	new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
1294 		struct intel_bw_state *new_bw_state;
1304 		new_bw_state = intel_atomic_get_bw_state(state);
1305 		if (IS_ERR(new_bw_state))
1306 			return PTR_ERR(new_bw_state);
1308 		new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1309 		new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1316 			    new_bw_state->data_rate[crtc->pipe],
1317 			    new_bw_state->num_active_planes[crtc->pipe]);
1327 	struct intel_bw_state *new_bw_state;
1340 	new_bw_state = intel_atomic_get_new_bw_state(state);
1342 	if (new_bw_state &&
1344 	     intel_can_enable_sagv(i915, new_bw_state) ||
1345 	     new_bw_state->force_check_qgv))
1355 	ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
1359 	new_bw_state->force_check_qgv = false;