i915/display/intel_bw.c

40 static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
47 	val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
55 	val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
62 	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
66 	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
75 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
83 	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
90 	sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),
103 static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
110 	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
149 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
154 	if (DISPLAY_VER(dev_priv) >= 14)
158 	ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
165 		drm_err(&dev_priv->drm,
171 	dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ?
177 static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
183 	val = intel_uncore_read(&dev_priv->uncore,
185 	val2 = intel_uncore_read(&dev_priv->uncore,
201 intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
205 	if (DISPLAY_VER(dev_priv) >= 14)
206 		return mtl_read_qgv_point_info(dev_priv, sp, point);
207 	else if (IS_DG1(dev_priv))
208 		return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
210 		return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
213 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
217 	const struct dram_info *dram_info = &dev_priv->dram_info;
223 	if (DISPLAY_VER(dev_priv) >= 14) {
248 	} else if (DISPLAY_VER(dev_priv) >= 12) {
263 			if (IS_ROCKETLAKE(dev_priv)) {
282 	} else if (DISPLAY_VER(dev_priv) == 11) {
283 		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
287 	if (drm_WARN_ON(&dev_priv->drm,
294 		ret = intel_read_qgv_point_info(dev_priv, sp, i);
296 			drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i);
300 		drm_dbg_kms(&dev_priv->drm,
307 		ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
309 			drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
314 			drm_dbg_kms(&dev_priv->drm,
390 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
394 	int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
398 	int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
401 	ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
403 		drm_dbg_kms(&dev_priv->drm,
414 		struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
441 			drm_dbg_kms(&dev_priv->drm,
452 		dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
454 		dev_priv->display.sagv.status = I915_SAGV_ENABLED;
459 static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
462 	const struct dram_info *dram_info = &dev_priv->dram_info;
464 	int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
469 	int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
472 	ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
474 		drm_dbg_kms(&dev_priv->drm,
479 	if (DISPLAY_VER(dev_priv) < 14 &&
485 	if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
488 	if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
489 		drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
506 		struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
514 			bi_next = &dev_priv->display.bw.max[i + 1];
546 			drm_dbg_kms(&dev_priv->drm,
557 			drm_dbg_kms(&dev_priv->drm,
569 		dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
571 		dev_priv->display.sagv.status = I915_SAGV_ENABLED;
601 static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
611 	for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
613 			&dev_priv->display.bw.max[i];
629 static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
639 	for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
641 			&dev_priv->display.bw.max[i];
657 static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
661 			&dev_priv->display.bw.max[0];
682 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
684 	if (!HAS_DISPLAY(dev_priv))
687 	if (DISPLAY_VER(dev_priv) >= 14)
688 		tgl_get_bw_info(dev_priv, &mtl_sa_info);
689 	else if (IS_DG2(dev_priv))
690 		dg2_get_bw_info(dev_priv);
691 	else if (IS_ALDERLAKE_P(dev_priv))
692 		tgl_get_bw_info(dev_priv, &adlp_sa_info);
693 	else if (IS_ALDERLAKE_S(dev_priv))
694 		tgl_get_bw_info(dev_priv, &adls_sa_info);
695 	else if (IS_ROCKETLAKE(dev_priv))
696 		tgl_get_bw_info(dev_priv, &rkl_sa_info);
697 	else if (DISPLAY_VER(dev_priv) == 12)
698 		tgl_get_bw_info(dev_priv, &tgl_sa_info);
699 	else if (DISPLAY_VER(dev_priv) == 11)
700 		icl_get_bw_info(dev_priv, &icl_sa_info);
766 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
772 	for_each_pipe(dev_priv, pipe)
778 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
784 	for_each_pipe(dev_priv, pipe)
787 	if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
796 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
799 	bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
807 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
810 	bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
818 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
821 	bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
1206 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1215 	if (DISPLAY_VER(dev_priv) < 9)
1234 	if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
1240 	old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
1241 	new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
1269 	drm_dbg_kms(&dev_priv->drm,