Lines Matching defs:wm
231 mutex_lock(&dev_priv->display.wm.wm_mutex);
234 dev_priv->display.wm.vlv.cxsr = enable;
236 dev_priv->display.wm.g4x.cxsr = enable;
237 mutex_unlock(&dev_priv->display.wm.wm_mutex);
265 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
529 * @wm: chip FIFO params
547 const struct intel_watermark_params *wm,
561 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
562 wm->guard_size;
569 if (wm_size > wm->max_wm)
570 wm_size = wm->max_wm;
572 wm_size = wm->default_wm;
636 unsigned int wm;
654 wm = intel_calculate_wm(dev_priv, pixel_rate,
660 reg |= FW_WM(wm, SR);
665 wm = intel_calculate_wm(dev_priv, pixel_rate,
670 FW_WM(wm, CURSOR_SR));
673 wm = intel_calculate_wm(dev_priv, pixel_rate,
677 intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
680 wm = intel_calculate_wm(dev_priv, pixel_rate,
686 reg |= FW_WM(wm, HPLL_CURSOR);
714 const struct g4x_wm_values *wm)
719 trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm);
722 FW_WM(wm->sr.plane, SR) |
723 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
724 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
725 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
727 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
728 FW_WM(wm->sr.fbc, FBC_SR) |
729 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
730 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
731 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
732 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
734 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
735 FW_WM(wm->sr.cursor, CURSOR_SR) |
736 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
737 FW_WM(wm->hpll.plane, HPLL_SR));
746 const struct vlv_wm_values *wm)
751 trace_vlv_wm(intel_crtc_for_pipe(dev_priv, pipe), wm);
754 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
755 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
756 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
757 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
772 FW_WM(wm->sr.plane, SR) |
773 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
774 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
775 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
777 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
778 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
779 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
781 FW_WM(wm->sr.cursor, CURSOR_SR));
785 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
786 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
788 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
789 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
791 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
792 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
794 FW_WM(wm->sr.plane >> 9, SR_HI) |
795 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
796 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
797 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
798 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
799 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
800 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
801 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
802 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
803 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
806 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
807 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
809 FW_WM(wm->sr.plane >> 9, SR_HI) |
810 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
811 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
812 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
813 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
814 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
815 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
826 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
827 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
828 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
830 dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
883 unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;
884 unsigned int pixel_rate, htotal, cpp, width, wm;
910 wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
913 wm = intel_wm_method1(pixel_rate, cpp, latency);
920 wm = min(small, large);
923 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
926 wm = DIV_ROUND_UP(wm, 64) + 2;
928 return min_t(unsigned int, wm, USHRT_MAX);
937 for (; level < dev_priv->display.wm.num_levels; level++) {
938 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
956 for (; level < dev_priv->display.wm.num_levels; level++) {
957 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
986 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
987 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
988 int wm, max_wm;
990 wm = g4x_compute_wm(crtc_state, plane_state, level);
993 if (wm > max_wm)
996 dirty |= raw->plane[plane_id] != wm;
997 raw->plane[plane_id] = wm;
1003 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1008 * FBC wm is not mandatory as we
1011 if (wm > max_wm)
1012 wm = USHRT_MAX;
1014 dirty |= raw->fbc != wm;
1015 raw->fbc = wm;
1029 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1030 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1031 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1036 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1037 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1046 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1056 if (level >= dev_priv->display.wm.num_levels)
1072 wm_state->wm.plane[plane_id] = USHRT_MAX;
1110 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1120 raw = &crtc_state->wm.g4x.raw[level];
1122 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1128 raw = &crtc_state->wm.g4x.raw[level];
1139 raw = &crtc_state->wm.g4x.raw[level];
1203 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1204 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1205 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1224 intermediate->wm.plane[plane_id] =
1225 max(optimal->wm.plane[plane_id],
1226 active->wm.plane[plane_id]);
1228 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1272 new_crtc_state->wm.need_postvbl_update = true;
1278 struct g4x_wm_values *wm)
1283 wm->cxsr = true;
1284 wm->hpll_en = true;
1285 wm->fbc_en = true;
1288 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1294 wm->cxsr = false;
1296 wm->hpll_en = false;
1298 wm->fbc_en = false;
1304 wm->cxsr = false;
1305 wm->hpll_en = false;
1306 wm->fbc_en = false;
1310 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1313 wm->pipe[pipe] = wm_state->wm;
1314 if (crtc->active && wm->cxsr)
1315 wm->sr = wm_state->sr;
1316 if (crtc->active && wm->hpll_en)
1317 wm->hpll = wm_state->hpll;
1323 struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;
1349 mutex_lock(&dev_priv->display.wm.wm_mutex);
1350 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1352 mutex_unlock(&dev_priv->display.wm.wm_mutex);
1362 if (!crtc_state->wm.need_postvbl_update)
1365 mutex_lock(&dev_priv->display.wm.wm_mutex);
1366 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1368 mutex_unlock(&dev_priv->display.wm.wm_mutex);
1390 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1392 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1;
1395 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1396 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1398 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;
1410 unsigned int pixel_rate, htotal, cpp, width, wm;
1412 if (dev_priv->display.wm.pri_latency[level] == 0)
1430 wm = 63;
1432 wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
1433 dev_priv->display.wm.pri_latency[level] * 10);
1436 return min_t(unsigned int, wm, USHRT_MAX);
1450 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1451 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1534 for (; level < dev_priv->display.wm.num_levels; level++) {
1538 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1545 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1547 if (wm > fifo_size)
1550 return fifo_size - wm;
1563 for (; level < dev_priv->display.wm.num_levels; level++) {
1564 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1587 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
1588 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1589 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1592 if (wm > max_wm)
1595 dirty |= raw->plane[plane_id] != wm;
1596 raw->plane[plane_id] = wm;
1607 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1608 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1609 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1618 &crtc_state->wm.vlv.raw[level];
1620 &crtc_state->wm.vlv.fifo_state;
1637 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1639 &crtc_state->wm.vlv.fifo_state;
1646 wm_state->num_levels = dev_priv->display.wm.num_levels;
1655 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1662 wm_state->wm[level].plane[plane_id] =
1732 &old_crtc_state->wm.vlv.fifo_state;
1734 &crtc_state->wm.vlv.fifo_state;
1761 &crtc_state->wm.vlv.fifo_state;
1858 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
1859 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
1860 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
1879 intermediate->wm[level].plane[plane_id] =
1880 min(optimal->wm[level].plane[plane_id],
1881 active->wm[level].plane[plane_id]);
1898 new_crtc_state->wm.need_postvbl_update = true;
1904 struct vlv_wm_values *wm)
1909 wm->level = dev_priv->display.wm.num_levels - 1;
1910 wm->cxsr = true;
1913 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1919 wm->cxsr = false;
1922 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1926 wm->cxsr = false;
1929 wm->level = VLV_WM_LEVEL_PM2;
1932 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1935 wm->pipe[pipe] = wm_state->wm[wm->level];
1936 if (crtc->active && wm->cxsr)
1937 wm->sr = wm_state->sr[wm->level];
1939 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1940 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1941 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1942 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1948 struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv;
1986 mutex_lock(&dev_priv->display.wm.wm_mutex);
1987 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
1989 mutex_unlock(&dev_priv->display.wm.wm_mutex);
1999 if (!crtc_state->wm.need_postvbl_update)
2002 mutex_lock(&dev_priv->display.wm.wm_mutex);
2003 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2005 mutex_unlock(&dev_priv->display.wm.wm_mutex);
2038 "self-refresh entries: %d, wm: %d\n",
2590 u16 pri_latency = dev_priv->display.wm.pri_latency[level];
2591 u16 spr_latency = dev_priv->display.wm.spr_latency[level];
2592 u16 cur_latency = dev_priv->display.wm.cur_latency[level];
2616 static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
2620 i915->display.wm.num_levels = 5;
2624 wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
2625 if (wm[0] == 0)
2626 wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
2627 wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
2628 wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
2629 wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
2630 wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
2633 static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
2637 i915->display.wm.num_levels = 4;
2641 wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
2642 wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
2643 wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
2644 wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
2647 static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
2651 i915->display.wm.num_levels = 3;
2656 wm[0] = 7;
2657 wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
2658 wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
2662 u16 wm[5])
2666 wm[0] = 13;
2670 u16 wm[5])
2674 wm[0] = 13;
2678 u16 wm[5], u16 min)
2682 if (wm[0] >= min)
2685 wm[0] = max(wm[0], min);
2686 for (level = 1; level < dev_priv->display.wm.num_levels; level++)
2687 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
2700 changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12);
2701 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12);
2702 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12);
2709 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
2710 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
2711 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
2727 if (dev_priv->display.wm.pri_latency[3] == 0 &&
2728 dev_priv->display.wm.spr_latency[3] == 0 &&
2729 dev_priv->display.wm.cur_latency[3] == 0)
2732 dev_priv->display.wm.pri_latency[3] = 0;
2733 dev_priv->display.wm.spr_latency[3] = 0;
2734 dev_priv->display.wm.cur_latency[3] = 0;
2738 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
2739 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
2740 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
2746 hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
2748 snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
2750 ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
2752 memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,
2753 sizeof(dev_priv->display.wm.pri_latency));
2754 memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency,
2755 sizeof(dev_priv->display.wm.pri_latency));
2757 intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency);
2758 intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency);
2760 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
2761 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
2762 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
2785 if (!ilk_validate_wm_level(dev_priv, 0, &max, &pipe_wm->wm[0])) {
2809 pipe_wm = &crtc_state->wm.ilk.optimal;
2824 usable_level = dev_priv->display.wm.num_levels - 1;
2834 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2836 pristate, sprstate, curstate, &pipe_wm->wm[0]);
2844 struct intel_wm_level *wm = &pipe_wm->wm[level];
2847 pristate, sprstate, curstate, wm);
2854 if (!ilk_validate_wm_level(dev_priv, level, &max, wm)) {
2855 memset(wm, 0, sizeof(*wm));
2876 struct intel_pipe_wm *a = &new_crtc_state->wm.ilk.intermediate;
2877 const struct intel_pipe_wm *b = &old_crtc_state->wm.ilk.optimal;
2885 *a = new_crtc_state->wm.ilk.optimal;
2895 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
2896 struct intel_wm_level *a_wm = &a->wm[level];
2897 const struct intel_wm_level *b_wm = &b->wm[level];
2919 if (memcmp(a, &new_crtc_state->wm.ilk.optimal, sizeof(*a)) != 0)
2920 new_crtc_state->wm.need_postvbl_update = true;
2937 const struct intel_pipe_wm *active = &crtc->wm.active.ilk;
2938 const struct intel_wm_level *wm = &active->wm[level];
2948 if (!wm->enable)
2951 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2952 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2953 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2954 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2966 int level, num_levels = dev_priv->display.wm.num_levels;
2979 struct intel_wm_level *wm = &merged->wm[level];
2981 ilk_merge_wm_level(dev_priv, level, wm);
2984 wm->enable = false;
2985 else if (!ilk_validate_wm_level(dev_priv, level, max, wm))
2993 if (wm->fbc_val > max->fbc) {
2994 if (wm->enable)
2996 wm->fbc_val = 0;
3004 struct intel_wm_level *wm = &merged->wm[level];
3006 wm->enable = false;
3014 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3024 return dev_priv->display.wm.pri_latency[level];
3044 r = &merged->wm[level];
3078 const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk;
3079 const struct intel_wm_level *r = &pipe_wm->wm[0];
3102 for (level = 1; level < dev_priv->display.wm.num_levels; level++) {
3103 if (r1->wm[level].enable)
3105 if (r2->wm[level].enable)
3177 struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
3211 struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
3260 dev_priv->display.wm.hw = *results;
3275 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3277 if (!wm->pipe_enabled)
3280 config->sprites_enabled |= wm->sprites_enabled;
3281 config->sprites_scaled |= wm->sprites_scaled;
3325 mutex_lock(&dev_priv->display.wm.wm_mutex);
3326 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
3328 mutex_unlock(&dev_priv->display.wm.wm_mutex);
3338 if (!crtc_state->wm.need_postvbl_update)
3341 mutex_lock(&dev_priv->display.wm.wm_mutex);
3342 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
3344 mutex_unlock(&dev_priv->display.wm.wm_mutex);
3351 struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
3353 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
3371 active->wm[0].enable = true;
3372 active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
3373 active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
3374 active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
3383 for (level = 0; level < dev_priv->display.wm.num_levels; level++)
3384 active->wm[level].enable = true;
3387 crtc->wm.active.ilk = *active;
3443 if (!dev_priv->display.funcs.wm->optimize_watermarks)
3479 crtc_state->wm.need_postvbl_update = true;
3482 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
3518 struct g4x_wm_values *wm)
3523 wm->sr.plane = _FW_WM(tmp, SR);
3524 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
3525 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
3526 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
3529 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
3530 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
3531 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
3532 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
3533 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
3534 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
3537 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
3538 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3539 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
3540 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
3544 struct vlv_wm_values *wm)
3552 wm->ddl[pipe].plane[PLANE_PRIMARY] =
3554 wm->ddl[pipe].plane[PLANE_CURSOR] =
3556 wm->ddl[pipe].plane[PLANE_SPRITE0] =
3558 wm->ddl[pipe].plane[PLANE_SPRITE1] =
3563 wm->sr.plane = _FW_WM(tmp, SR);
3564 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
3565 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
3566 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
3569 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
3570 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
3571 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
3574 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3578 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
3579 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
3582 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
3583 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
3586 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
3587 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
3590 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3591 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3592 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3593 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
3594 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3595 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3596 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
3597 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3598 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3599 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
3602 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
3603 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
3606 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3607 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3608 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3609 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
3610 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3611 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3612 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
3621 struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
3624 g4x_read_wm_values(dev_priv, wm);
3626 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
3631 struct g4x_wm_state *active = &crtc->wm.active.g4x;
3637 active->cxsr = wm->cxsr;
3638 active->hpll_en = wm->hpll_en;
3639 active->fbc_en = wm->fbc_en;
3641 active->sr = wm->sr;
3642 active->hpll = wm->hpll;
3645 active->wm.plane[plane_id] =
3646 wm->pipe[pipe].plane[plane_id];
3649 if (wm->cxsr && wm->hpll_en)
3651 else if (wm->cxsr)
3657 raw = &crtc_state->wm.g4x.raw[level];
3659 raw->plane[plane_id] = active->wm.plane[plane_id];
3665 raw = &crtc_state->wm.g4x.raw[level];
3675 raw = &crtc_state->wm.g4x.raw[level];
3690 crtc_state->wm.g4x.optimal = *active;
3691 crtc_state->wm.g4x.intermediate = *active;
3696 wm->pipe[pipe].plane[PLANE_PRIMARY],
3697 wm->pipe[pipe].plane[PLANE_CURSOR],
3698 wm->pipe[pipe].plane[PLANE_SPRITE0]);
3703 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
3706 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
3708 str_yes_no(wm->cxsr), str_yes_no(wm->hpll_en),
3709 str_yes_no(wm->fbc_en));
3717 mutex_lock(&dev_priv->display.wm.wm_mutex);
3732 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
3734 &crtc_state->wm.g4x.raw[level];
3751 crtc_state->wm.g4x.intermediate =
3752 crtc_state->wm.g4x.optimal;
3753 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
3758 mutex_unlock(&dev_priv->display.wm.wm_mutex);
3769 struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
3773 vlv_read_wm_values(dev_priv, wm);
3775 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3776 wm->level = VLV_WM_LEVEL_PM2;
3783 wm->level = VLV_WM_LEVEL_PM5;
3803 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM5 + 1;
3807 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3816 struct vlv_wm_state *active = &crtc->wm.active.vlv;
3818 &crtc_state->wm.vlv.fifo_state;
3825 active->num_levels = wm->level + 1;
3826 active->cxsr = wm->cxsr;
3830 &crtc_state->wm.vlv.raw[level];
3832 active->sr[level].plane = wm->sr.plane;
3833 active->sr[level].cursor = wm->sr.cursor;
3836 active->wm[level].plane[plane_id] =
3837 wm->pipe[pipe].plane[plane_id];
3840 vlv_invert_wm_value(active->wm[level].plane[plane_id],
3850 crtc_state->wm.vlv.optimal = *active;
3851 crtc_state->wm.vlv.intermediate = *active;
3856 wm->pipe[pipe].plane[PLANE_PRIMARY],
3857 wm->pipe[pipe].plane[PLANE_CURSOR],
3858 wm->pipe[pipe].plane[PLANE_SPRITE0],
3859 wm->pipe[pipe].plane[PLANE_SPRITE1]);
3864 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3872 mutex_lock(&dev_priv->display.wm.wm_mutex);
3887 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
3889 &crtc_state->wm.vlv.raw[level];
3903 crtc_state->wm.vlv.intermediate =
3904 crtc_state->wm.vlv.optimal;
3905 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
3910 mutex_unlock(&dev_priv->display.wm.wm_mutex);
3937 struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
4017 dev_priv->display.funcs.wm = &ilk_wm_funcs;
4020 dev_priv->display.funcs.wm = &vlv_wm_funcs;
4023 dev_priv->display.funcs.wm = &g4x_wm_funcs;
4034 dev_priv->display.funcs.wm = &nop_funcs;
4036 dev_priv->display.funcs.wm = &pnv_wm_funcs;
4039 dev_priv->display.funcs.wm = &i965_wm_funcs;
4041 dev_priv->display.funcs.wm = &i9xx_wm_funcs;
4044 dev_priv->display.funcs.wm = &i845_wm_funcs;
4046 dev_priv->display.funcs.wm = &i9xx_wm_funcs;
4050 dev_priv->display.funcs.wm = &nop_funcs;