i915/display/i9xx_wm.c

144 		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
145 		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
146 		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
148 		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
149 		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
150 		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
152 		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
158 		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
159 		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
161 		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
164 		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
165 		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
172 		was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
175 		intel_uncore_write(&dev_priv->uncore, INSTPM, val);
176 		intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
272 		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
273 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
278 		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
279 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
284 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
285 		dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
303 	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
319 	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
336 	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
658 		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
661 		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
669 		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK,
677 		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
684 		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
687 		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
721 	intel_uncore_write(&dev_priv->uncore, DSPFW1,
726 	intel_uncore_write(&dev_priv->uncore, DSPFW2,
733 	intel_uncore_write(&dev_priv->uncore, DSPFW3,
739 	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
753 		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
765 	intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
766 	intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
767 	intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
768 	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
769 	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
771 	intel_uncore_write(&dev_priv->uncore, DSPFW1,
776 	intel_uncore_write(&dev_priv->uncore, DSPFW2,
780 	intel_uncore_write(&dev_priv->uncore, DSPFW3,
784 		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
787 		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
790 		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
793 		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
805 		intel_uncore_write(&dev_priv->uncore, DSPFW7,
808 		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
818 	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
1757 	struct intel_uncore *uncore = &dev_priv->uncore;
1778 	 * uncore.lock serves a double purpose here. It allows us to
1786 	spin_lock(&uncore->lock);
1790 		dsparb = intel_uncore_read_fw(uncore, DSPARB);
1791 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
1803 		intel_uncore_write_fw(uncore, DSPARB, dsparb);
1804 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
1807 		dsparb = intel_uncore_read_fw(uncore, DSPARB);
1808 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
1820 		intel_uncore_write_fw(uncore, DSPARB, dsparb);
1821 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
1824 		dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
1825 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
1837 		intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
1838 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
1844 	intel_uncore_posting_read_fw(uncore, DSPARB);
1846 	spin_unlock(&uncore->lock);
2068 	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
2072 	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
2075 	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2216 			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
2219 			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
2233 	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2234 	intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
2254 	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
2260 	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2622 	sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD);
2639 	sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD);
2653 	mltr = intel_uncore_read(&i915->uncore, MLTR_ILK);
3182 		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
3187 		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
3192 		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
3221 		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
3223 		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
3225 		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
3229 			intel_uncore_rmw(&dev_priv->uncore, WM_MISC, WM_MISC_DATA_PARTITION_5_6,
3233 			intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,
3239 		intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, DISP_FBC_WM_DIS,
3244 		intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
3248 			intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
3250 			intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
3254 		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
3256 		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
3258 		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
3356 	hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
3522 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
3528 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
3536 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
3550 		tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
3562 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
3568 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
3573 	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
3577 		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
3581 		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
3585 		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
3589 		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
3601 		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
3605 		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
3626 	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
3775 	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3925 	intel_uncore_rmw(&dev_priv->uncore, WM3_LP_ILK, WM_LP_ENABLE, 0);
3926 	intel_uncore_rmw(&dev_priv->uncore, WM2_LP_ILK, WM_LP_ENABLE, 0);
3927 	intel_uncore_rmw(&dev_priv->uncore, WM1_LP_ILK, WM_LP_ENABLE, 0);
3945 	hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
3946 	hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
3947 	hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
3949 	hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
3951 		hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
3952 		hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
3956 		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) &
3960 		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) &
3965 		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);