i915/display/i9xx_plane.c

12 #include "i9xx_plane.h"
111 			       enum i9xx_plane_id i9xx_plane)
117 		return i9xx_plane == PLANE_A; /* tied to pipe A */
119 		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
120 			i9xx_plane == PLANE_C;
122 		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
124 		return i9xx_plane == PLANE_A;
128 					enum i9xx_plane_id i9xx_plane)
130 	if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
139 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
142 		return i9xx_plane == PLANE_B;
146 		return i9xx_plane == PLANE_C;
148 		return i9xx_plane == PLANE_B ||
149 			i9xx_plane == PLANE_C;
423 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
425 	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
439 		intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
441 		intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
451 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
465 	if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
471 		intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
473 		intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
475 		intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
479 		intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
482 		intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
484 		intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
493 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
496 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
499 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
521 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
536 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
539 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
541 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
553 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
558 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
560 	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
572 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
574 	intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
606 	ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
616 	ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
626 	ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
636 	ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
667 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
682 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
751 		if (plane->i9xx_plane == PLANE_C)
798 		plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
800 		plane->i9xx_plane = (enum i9xx_plane_id) pipe;
804 	intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);
906 					       plane_name(plane->i9xx_plane));
982 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1005 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
1026 		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
1027 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1031 					       DSPTILEOFF(i9xx_plane));
1034 					       DSPLINOFF(i9xx_plane));
1035 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1038 		base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
1048 	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
1071 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1087 		intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
1089 		intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);