i915/display/i9xx_plane.c

110 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
113 	if (!HAS_FBC(dev_priv))
116 	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
118 	else if (IS_IVYBRIDGE(dev_priv))
121 	else if (DISPLAY_VER(dev_priv) >= 4)
127 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
130 	if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
131 		return dev_priv->display.fbc[INTEL_FBC_A];
138 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
141 	if (IS_CHERRYVIEW(dev_priv))
143 	else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
145 	else if (DISPLAY_VER(dev_priv) == 4)
155 	struct drm_i915_private *dev_priv =
163 	if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
164 	    IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
212 	if (DISPLAY_VER(dev_priv) >= 4 &&
227 	struct drm_i915_private *dev_priv =
246 	if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
251 	if (DISPLAY_VER(dev_priv) >= 4)
268 	if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
274 				drm_dbg_kms(&dev_priv->drm,
292 	if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
305 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
306 		drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
307 	} else if (DISPLAY_VER(dev_priv) >= 4 &&
309 		drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
356 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
365 	if (DISPLAY_VER(dev_priv) < 5)
422 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
425 	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
428 	if (DISPLAY_VER(dev_priv) < 4) {
439 		intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
441 		intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
450 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
460 	if (DISPLAY_VER(dev_priv) >= 4)
465 	if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
471 		intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
473 		intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
475 		intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
478 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
479 		intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
481 	} else if (DISPLAY_VER(dev_priv) >= 4) {
482 		intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
484 		intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
493 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
495 	if (DISPLAY_VER(dev_priv) >= 4)
496 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
499 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
520 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
536 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
538 	if (DISPLAY_VER(dev_priv) >= 4)
539 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
541 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
550 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
558 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
560 	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
570 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
574 	intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
665 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
678 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
682 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
686 	if (DISPLAY_VER(dev_priv) >= 5)
691 	intel_display_power_put(dev_priv, power_domain, wakeref);
743 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
745 	if (DISPLAY_VER(dev_priv) >= 3) {
777 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
796 	if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 &&
797 	    INTEL_NUM_PIPES(dev_priv) == 2)
804 	intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);
806 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
809 	} else if (DISPLAY_VER(dev_priv) >= 4) {
823 		if (IS_IVYBRIDGE(dev_priv)) {
835 	if (DISPLAY_VER(dev_priv) >= 4)
840 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
842 	else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
844 	else if (IS_IVYBRIDGE(dev_priv))
849 	if (HAS_GMCH(dev_priv)) {
850 		if (DISPLAY_VER(dev_priv) >= 4)
855 		if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
861 	if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
871 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
875 	} else if (IS_BROADWELL(dev_priv)) {
880 	} else if (DISPLAY_VER(dev_priv) >= 7) {
884 	} else if (DISPLAY_VER(dev_priv) >= 5) {
890 	modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
892 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
893 		ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
900 		ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
913 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
917 	} else if (DISPLAY_VER(dev_priv) >= 4) {
924 	if (DISPLAY_VER(dev_priv) >= 4)
980 	struct drm_i915_private *dev_priv = to_i915(dev);
997 		drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
1005 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
1007 	if (DISPLAY_VER(dev_priv) >= 4) {
1017 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
1025 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1026 		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
1027 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1028 	} else if (DISPLAY_VER(dev_priv) >= 4) {
1030 			offset = intel_de_read(dev_priv,
1033 			offset = intel_de_read(dev_priv,
1035 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1038 		base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
1042 	drm_WARN_ON(&dev_priv->drm, offset != 0);
1044 	val = intel_de_read(dev_priv, PIPESRC(pipe));
1048 	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
1055 	drm_dbg_kms(&dev_priv->drm,
1067 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1086 	if (DISPLAY_VER(dev_priv) >= 4)
1087 		intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
1089 		intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);