i915/display/g4x_hdmi.c

30 	struct drm_i915_private *dev_priv = to_i915(dev);
39 	if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
54 	if (HAS_PCH_CPT(dev_priv))
56 	else if (IS_CHERRYVIEW(dev_priv))
61 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
62 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
68 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
73 	wakeref = intel_display_power_get_if_enabled(dev_priv,
78 	ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
80 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
157 	struct drm_i915_private *dev_priv = to_i915(dev);
163 	tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
187 	if (!HAS_PCH_SPLIT(dev_priv) &&
224 	struct drm_i915_private *dev_priv = to_i915(dev);
228 	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
232 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
233 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
284 	struct drm_i915_private *dev_priv = to_i915(dev);
288 	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
296 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
297 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
298 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
299 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
310 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
312 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
318 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
319 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
320 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
321 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
331 	struct drm_i915_private *dev_priv = to_i915(dev);
337 	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
352 		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
359 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
360 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
366 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
367 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
369 		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
387 	struct drm_i915_private *dev_priv = to_i915(dev);
394 	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
397 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
398 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
405 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
410 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
411 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
419 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
420 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
421 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
422 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
425 		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
426 		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
428 		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
429 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
430 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
484 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
499 	vlv_wait_port_ready(dev_priv, dig_port, 0x0);
545 	struct drm_i915_private *dev_priv = to_i915(dev);
547 	vlv_dpio_get(dev_priv);
552 	vlv_dpio_put(dev_priv);
562 	struct drm_i915_private *dev_priv = to_i915(dev);
576 	vlv_wait_port_ready(dev_priv, dig_port, 0x0);
686 void g4x_hdmi_init(struct drm_i915_private *dev_priv,
694 	if (!assert_port_valid(dev_priv, port))
697 	if (!assert_hdmi_port_valid(dev_priv, port))
700 	devdata = intel_bios_encoder_data_lookup(dev_priv, port);
704 		drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n",
725 	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
731 	if (HAS_PCH_SPLIT(dev_priv)) {
739 	if (IS_CHERRYVIEW(dev_priv)) {
745 	} else if (IS_VALLEYVIEW(dev_priv)) {
752 		if (HAS_PCH_CPT(dev_priv))
754 		else if (HAS_PCH_IBX(dev_priv))
764 	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
766 	if (IS_CHERRYVIEW(dev_priv)) {
775 	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
781 	if (IS_G4X(dev_priv))