i915/display/g4x_dp.c

59 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
63 	if (IS_G4X(dev_priv)) {
66 	} else if (HAS_PCH_SPLIT(dev_priv)) {
69 	} else if (IS_CHERRYVIEW(dev_priv)) {
72 	} else if (IS_VALLEYVIEW(dev_priv)) {
91 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
120 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
128 	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
139 	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
142 		intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),
147 		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
159 		if (IS_CHERRYVIEW(dev_priv))
169 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
170 	bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
172 	I915_STATE_WARN(dev_priv, cur_state != state,
179 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
181 	bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
183 	I915_STATE_WARN(dev_priv, cur_state != state,
194 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
196 	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
198 	assert_edp_pll_disabled(dev_priv);
200 	drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
210 	intel_de_write(dev_priv, DP_A, intel_dp->DP);
211 	intel_de_posting_read(dev_priv, DP_A);
220 	if (IS_IRONLAKE(dev_priv))
221 		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
225 	intel_de_write(dev_priv, DP_A, intel_dp->DP);
226 	intel_de_posting_read(dev_priv, DP_A);
234 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
236 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
238 	assert_edp_pll_enabled(dev_priv);
240 	drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
244 	intel_de_write(dev_priv, DP_A, intel_dp->DP);
245 	intel_de_posting_read(dev_priv, DP_A);
249 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
254 	for_each_pipe(dev_priv, p) {
255 		u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
263 	drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
272 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
279 	val = intel_de_read(dev_priv, dp_reg);
284 	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
286 	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
287 		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
288 	else if (IS_CHERRYVIEW(dev_priv))
299 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
304 	wakeref = intel_display_power_get_if_enabled(dev_priv,
309 	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
312 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
335 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
346 	tmp = intel_de_read(dev_priv, intel_dp->output_reg);
350 	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
351 		u32 trans_dp = intel_de_read(dev_priv,
383 	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
392 		if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
412 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417 	if (drm_WARN_ON(&dev_priv->drm,
418 			(intel_de_read(dev_priv, intel_dp->output_reg) &
422 	drm_dbg_kms(&dev_priv->drm, "\n");
424 	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
425 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
432 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
433 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
436 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
437 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
444 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
449 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
450 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
456 		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
457 		intel_de_posting_read(dev_priv, intel_dp->output_reg);
460 		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
461 		intel_de_posting_read(dev_priv, intel_dp->output_reg);
463 		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
464 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
465 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
470 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
581 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
585 	vlv_dpio_get(dev_priv);
590 	vlv_dpio_put(dev_priv);
598 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
617 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
618 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
626 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
645 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
646 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
652 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
667 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
668 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
676 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
678 	u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
681 	if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
685 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
695 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
698 		if (IS_CHERRYVIEW(dev_priv))
701 		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
1028 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1041 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1042 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
1076 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1083 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1089 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1090 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
1128 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1135 	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1141 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1142 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
1205 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1206 	u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
1208 	return intel_de_read(dev_priv, SDEISR) & bit;
1213 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1231 	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
1236 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1237 	u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
1239 	return intel_de_read(dev_priv, DEISR) & bit;
1252 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1256 	if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
1265 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1268 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
1272 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1287 bool g4x_dp_init(struct drm_i915_private *dev_priv,
1296 	if (!assert_port_valid(dev_priv, port))
1299 	devdata = intel_bios_encoder_data_lookup(dev_priv, port);
1303 		drm_dbg_kms(&dev_priv->drm, "No VBT child device for DP-%c\n",
1323 	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1337 	if (IS_CHERRYVIEW(dev_priv)) {
1344 	} else if (IS_VALLEYVIEW(dev_priv)) {
1359 	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
1360 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
1365 	if (IS_CHERRYVIEW(dev_priv))
1367 	else if (IS_VALLEYVIEW(dev_priv))
1369 	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
1371 	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
1376 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
1377 	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
1389 	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
1390 	if (IS_CHERRYVIEW(dev_priv)) {
1400 	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
1404 	if (HAS_GMCH(dev_priv)) {