hisilicon/kirin/dw_drm_dsi.c

89 	struct mipi_phy_params phy;
122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
152 		phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
153 		phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
155 		if (phy->hstx_ckg_sel <= 7 &&
156 		    phy->hstx_ckg_sel >= 4)
157 			q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
191 			phy->pll_fbd_p = 0;
192 			phy->pll_pre_div1p = 1;
194 			phy->pll_fbd_p = n_pll;
195 			phy->pll_pre_div1p = 0;
198 		if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
199 			r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
202 			phy->pll_pre_p = 0;
203 			phy->pll_fbd_s = 0;
204 			phy->pll_fbd_div1f = 0;
205 			phy->pll_fbd_div5f = 1;
207 			phy->pll_pre_p = m_pll / (2 * r_pll);
208 			phy->pll_fbd_s = 0;
209 			phy->pll_fbd_div1f = 1;
210 			phy->pll_fbd_div5f = 0;
213 				phy->pll_pre_p =
215 				phy->pll_fbd_s =
218 				phy->pll_pre_p =
220 				phy->pll_fbd_s =
223 			phy->pll_fbd_div1f = 0;
224 			phy->pll_fbd_div5f = 0;
226 			phy->pll_pre_p = 0;
227 			phy->pll_fbd_s = 0;
228 			phy->pll_fbd_div1f = 0;
229 			phy->pll_fbd_div5f = 1;
246 			       struct mipi_phy_params *phy)
252 	memset(phy, 0, sizeof(*phy));
254 	phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
260 	phy->clk_t_lpx = ROUND(50, 8 * ui);
261 	phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
263 	phy->clk_t_hs_zero = ROUND(262, 8 * ui);
264 	phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
265 	phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
266 	if (phy->clk_t_wakeup > 0xff)
267 		phy->clk_t_wakeup = 0xff;
268 	phy->data_t_wakeup = phy->clk_t_wakeup;
269 	phy->data_t_lpx = phy->clk_t_lpx;
270 	phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
271 	phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
272 	phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
273 	phy->data_t_ta_go = 3;
274 	phy->data_t_ta_get = 4;
276 	phy->pll_enbwt = 1;
277 	phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
278 	phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
279 	phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
280 	phy->hs2lp_time = phy->clkhs2lp_time;
281 	phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
282 	phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
283 				phy->clkhs2lp_time;
285 	phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
286 	phy->clk_division =
287 		DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
310  * dsi phy reg write function
332 			      struct mipi_phy_params *phy,
338 	 * Set lane value and phy stop wait time.
344 	 * Set phy clk division.
346 	val = readl(base + CLKMGR_CFG) | phy->clk_division;
352 	dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
353 	dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
355 		       phy->clkhs2lp_time);
357 		       phy->clklp2hs_time);
359 		       phy->data_to_clk_delay);
361 		       phy->clk_to_data_delay);
365 			     struct mipi_phy_params *phy,
372 	/* phy timer setting */
373 	dsi_set_phy_timer(base, phy, lanes);
376 	 * Reset to clean up phy tst params.
387 	dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
388 	dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
389 	dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
390 	dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
391 	dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
398 		dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
400 				phy->data_t_hs_prepare);
401 		dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
402 		dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
403 		dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
404 		dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
405 		dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
412 	dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
413 	val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
414 				(phy->pll_fbd_2p << 1) + phy->pll_enbwt;
416 	dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
417 	dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
418 	val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
420 	val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
421 		phy->pll_lpf_cs;
432 	 * wait for phy's clock ready
541 	struct mipi_phy_params *phy = &dsi->phy;
548 	 * count phy params
551 	dsi_get_phy_params(dphy_req_kHz, phy);
556 	/* set dsi phy params */
557 	dsi_set_mipi_phy(base, phy, dsi->lanes);
560 	dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
569 			 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
614 	struct mipi_phy_params phy;
619 	memset(&phy, 0, sizeof(phy));
621 	act_kHz = dsi_calc_phy_rate(req_kHz, &phy);