Lines Matching refs:dpll
107 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
158 dpll = DPLL_VGA_MODE_DIS;
160 dpll |= DPLLB_MODE_LVDS;
161 dpll |= DPLL_DVO_HIGH_SPEED;
163 dpll |= DPLLB_MODE_DAC_SERIAL;
167 dpll |= DPLL_DVO_HIGH_SPEED;
168 dpll |=
173 dpll |= (1 << (clock.p1 - 1)) << 16;
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
191 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
192 dpll |= 3;
194 dpll |= PLL_REF_INPUT_DREFCLK;
209 dpll |= DPLL_VCO_ENABLE;
218 if (dpll & DPLL_VCO_ENABLE) {
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
221 REG_READ(map->dpll);
255 REG_WRITE(map->dpll, dpll);
256 REG_READ(map->dpll);
261 REG_WRITE(map->dpll, dpll);
263 REG_READ(map->dpll);
310 u32 dpll;
317 dpll = REG_READ(map->dpll);
318 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
325 dpll = p->dpll;
327 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
342 ffs((dpll &
347 if ((dpll & PLL_REF_INPUT_MASK) ==
354 if (dpll & PLL_P1_DIVIDE_BY_TWO)
358 ((dpll &
362 if (dpll & PLL_P2_DIVIDE_BY_4)