drm/gma500/cdv_intel_dp.c

268 	uint8_t link_status[DP_LINK_STATUS_SIZE];
1233 					      intel_dp->link_status,
1238 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1241 	return link_status[r - DP_LANE0_1_STATUS];
1245 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1252 	uint8_t l = cdv_intel_dp_link_status(link_status, i);
1258 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1265 	uint8_t l = cdv_intel_dp_link_status(link_status, i);
1281 		uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1282 		uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1302 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1307 	uint8_t l = cdv_intel_dp_link_status(link_status, i);
1314 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1320 		lane_status = cdv_intel_get_lane_status(link_status, lane);
1339 	lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
1344 		lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
1519 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1520 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1522 		if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1601 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1602 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1605 		if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {