drm/gma500/cdv_intel_dp.c

256 	uint32_t DP;
307  * If a CPU or PCH DP output is attached to an eDP panel, this function
599 	/* Must try at least 3 times according to DP spec */
1044 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1045 	intel_dp->DP |= intel_dp->color_range;
1048 		intel_dp->DP |= DP_SYNC_HS_HIGH;
1050 		intel_dp->DP |= DP_SYNC_VS_HIGH;
1052 	intel_dp->DP |= DP_LINK_TRAIN_OFF;
1056 		intel_dp->DP |= DP_PORT_WIDTH_1;
1059 		intel_dp->DP |= DP_PORT_WIDTH_2;
1062 		intel_dp->DP |= DP_PORT_WIDTH_4;
1066 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1078 		intel_dp->DP |= DP_ENHANCED_FRAMING;
1081 	/* CPT DP's pipe select is decided in TRANS_DP_CTL */
1083 		intel_dp->DP |= DP_PIPEB_SELECT;
1085 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
1086 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
1473 	uint32_t DP = intel_dp->DP;
1475 	DP |= DP_PORT_EN;
1476 	DP &= ~DP_LINK_TRAIN_MASK;
1478 	reg = DP;
1497 	reg = DP | DP_LINK_TRAIN_PAT_1;
1501 		DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1518 		DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1550 		DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1553 	intel_dp->DP = DP;
1563 	uint32_t DP = intel_dp->DP;
1570 	reg = DP | DP_LINK_TRAIN_PAT_2;
1574 		DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1587 			DRM_ERROR("failed to train DP, aborting\n");
1600 		DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1631 	reg = DP | DP_LINK_TRAIN_OFF;
1644 	uint32_t DP = intel_dp->DP;
1653 		DP &= ~DP_LINK_TRAIN_MASK;
1654 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1660 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1684  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1686  * \return true if DP port is connected.
1687  * \return false if DP port is disconnected.
1903 /* check the VBT to see whether the eDP is on DP-D port */
1926    DP/eDP. TODO - investigate if we can turn it back to normality