drm/exynos/exynos_drm_fimd.c

44 #define VIDOSD_A(win)		(VIDOSD_BASE + 0x00 + (win) * 16)
45 #define VIDOSD_B(win)		(VIDOSD_BASE + 0x04 + (win) * 16)
50 #define VIDOSD_C(win)		(VIDOSD_BASE + 0x08 + (win) * 16)
52 #define VIDOSD_D(win)		(VIDOSD_BASE + 0x0C + (win) * 16)
54 #define VIDWnALPHA0(win)	(VIDW_ALPHA + 0x00 + (win) * 8)
55 #define VIDWnALPHA1(win)	(VIDW_ALPHA + 0x04 + (win) * 8)
57 #define VIDWx_BUF_START(win, buf)	(VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_START_S(win, buf)	(VIDW_BUF_START_S(buf) + (win) * 8)
59 #define VIDWx_BUF_END(win, buf)		(VIDW_BUF_END(buf) + (win) * 8)
60 #define VIDWx_BUF_SIZE(win, buf)	(VIDW_BUF_SIZE(buf) + (win) * 4)
336 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
339 	u32 val = readl(ctx->regs + WINCON(win));
346 	writel(val, ctx->regs + WINCON(win));
350 						unsigned int win,
356 		val |= SHADOWCON_CHx_ENABLE(win);
358 		val &= ~SHADOWCON_CHx_ENABLE(win);
366 	unsigned int win, ch_enabled = 0;
380 	for (win = 0; win < WINDOWS_NR; win++) {
381 		u32 val = readl(ctx->regs + WINCON(win));
384 			fimd_enable_video_output(ctx, win, false);
387 				fimd_enable_shadow_channel_path(ctx, win,
594 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
617 	fimd_set_bits(ctx, BLENDEQx(win), mask, val);
620 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
638 	fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
647 	writel(val, ctx->regs + VIDOSD_C(win));
651 	writel(val, ctx->regs + VIDWnALPHA0(win));
655 	writel(val, ctx->regs + VIDWnALPHA1(win));
661 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
664 	struct exynos_drm_plane *plane = &ctx->planes[win];
681 	if (ctx->driver_data->has_limited_fmt && !win) {
724 		writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win));
727 		writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win));
743 	fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
746 	if (win != 0) {
747 		fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
748 		fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
752 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
761 	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
762 	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
769  * @win: window to protect registers for
773 				    unsigned int win, bool protect)
789 		bits = SHADOWCON_WINx_PROTECT(win);
839 	unsigned int win = plane->index;
852 	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
857 	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
872 	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
879 	writel(val, ctx->regs + VIDOSD_A(win));
891 	writel(val, ctx->regs + VIDOSD_B(win));
898 	if (win != 3 && win != 4) {
899 		u32 offset = VIDOSD_D(win);
900 		if (win == 0)
901 			offset = VIDOSD_C(win);
909 	fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
912 	if (win != 0)
913 		fimd_win_set_colkey(ctx, win);
915 	fimd_enable_video_output(ctx, win, true);
918 		fimd_enable_shadow_channel_path(ctx, win, true);
928 	unsigned int win = plane->index;
933 	fimd_enable_video_output(ctx, win, false);
936 		fimd_enable_shadow_channel_path(ctx, win, false);