drm/exynos/exynos5433_drm_decon.c

96 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
99 	val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
100 	writel(val, ctx->addr + reg);
105 	struct decon_context *ctx = crtc->ctx;
114 	writel(val, ctx->addr + DECON_VIDINTCON0);
116 	enable_irq(ctx->irq);
117 	if (!(ctx->out_type & I80_HW_TRG))
118 		enable_irq(ctx->te_irq);
125 	struct decon_context *ctx = crtc->ctx;
127 	if (!(ctx->out_type & I80_HW_TRG))
128 		disable_irq_nosync(ctx->te_irq);
129 	disable_irq_nosync(ctx->irq);
131 	writel(0, ctx->addr + DECON_VIDINTCON0);
135 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
143 	frm = readl(ctx->addr + DECON_CRFMID);
145 		status = readl(ctx->addr + DECON_VIDCON1);
147 		frm = readl(ctx->addr + DECON_CRFMID);
158 		if (!(ctx->crtc->i80_mode))
176 static void decon_setup_trigger(struct decon_context *ctx)
178 	if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
181 	if (!(ctx->out_type & I80_HW_TRG)) {
184 		       ctx->addr + DECON_TRIGCON);
189 	       | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
191 	if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
193 		DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
198 	struct decon_context *ctx = crtc->ctx;
203 	if (ctx->out_type & IFTYPE_HDMI) {
212 	decon_setup_trigger(ctx);
224 	writel(val, ctx->addr + DECON_VIDOUTCON0);
232 	writel(val, ctx->addr + DECON_VIDTCON2);
241 		writel(val, ctx->addr + DECON_VIDTCON00);
245 		writel(val, ctx->addr + DECON_VIDTCON01);
251 		writel(val, ctx->addr + DECON_VIDTCON10);
255 		writel(val, ctx->addr + DECON_VIDTCON11);
259 	decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
261 	decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
264 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
287 	decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
290 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
307 	decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
313 		decon_set_bits(ctx, DECON_VIDOSDxC(win),
315 		decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
319 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
322 	struct exynos_drm_plane *plane = &ctx->planes[win];
334 	val = readl(ctx->addr + DECON_WINCONx(win));
361 	DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
375 	decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
378 		decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
379 		decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
383 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
385 	decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
391 	struct decon_context *ctx = crtc->ctx;
393 	decon_shadow_protect(ctx, true);
405 	struct decon_context *ctx = crtc->ctx;
416 		writel(val, ctx->addr + DECON_VIDOSDxA(win));
420 		writel(val, ctx->addr + DECON_VIDOSDxB(win));
423 		writel(val, ctx->addr + DECON_VIDOSDxA(win));
427 		writel(val, ctx->addr + DECON_VIDOSDxB(win));
432 	writel(val, ctx->addr + DECON_VIDOSDxC(win));
436 	writel(val, ctx->addr + DECON_VIDOSDxD(win));
438 	writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
441 	writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
443 	if (!(ctx->out_type & IFTYPE_HDMI))
449 	writel(val, ctx->addr + DECON_VIDW0xADD2(win));
451 	decon_win_set_pixfmt(ctx, win, fb);
454 	decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
460 	struct decon_context *ctx = crtc->ctx;
463 	decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
468 	struct decon_context *ctx = crtc->ctx;
471 	spin_lock_irqsave(&ctx->vblank_lock, flags);
473 	decon_shadow_protect(ctx, false);
475 	decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
477 	ctx->frame_id = decon_get_frame_count(ctx, true);
481 	spin_unlock_irqrestore(&ctx->vblank_lock, flags);
484 static void decon_swreset(struct decon_context *ctx)
490 	writel(0, ctx->addr + DECON_VIDCON0);
491 	readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
494 	writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
495 	ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
500 	spin_lock_irqsave(&ctx->vblank_lock, flags);
501 	ctx->frame_id = 0;
502 	spin_unlock_irqrestore(&ctx->vblank_lock, flags);
504 	if (!(ctx->out_type & IFTYPE_HDMI))
507 	writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
508 	decon_set_bits(ctx, DECON_CMU,
510 	writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
512 	       ctx->addr + DECON_CRCCTRL);
517 	struct decon_context *ctx = crtc->ctx;
520 	ret = pm_runtime_resume_and_get(ctx->dev);
522 		DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
528 	decon_swreset(ctx);
530 	decon_commit(ctx->crtc);
535 	struct decon_context *ctx = crtc->ctx;
538 	if (!(ctx->out_type & I80_HW_TRG))
539 		synchronize_irq(ctx->te_irq);
540 	synchronize_irq(ctx->irq);
547 	for (i = ctx->first_win; i < WINDOWS_NR; i++)
548 		decon_disable_plane(crtc, &ctx->planes[i]);
550 	decon_swreset(ctx);
554 	pm_runtime_put_sync(ctx->dev);
559 	struct decon_context *ctx = dev_id;
561 	decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
568 	struct decon_context *ctx = crtc->ctx;
572 		ret = clk_prepare_enable(ctx->clks[i]);
577 	decon_shadow_protect(ctx, true);
579 		decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
580 	decon_shadow_protect(ctx, false);
582 	decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
589 		clk_disable_unprepare(ctx->clks[i]);
595 	struct decon_context *ctx = crtc->ctx;
597 	ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
599 	if (ctx->irq)
602 	dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
622 	struct decon_context *ctx = dev_get_drvdata(dev);
629 	ctx->drm_dev = drm_dev;
631 	for (win = ctx->first_win; win < WINDOWS_NR; win++) {
632 		ctx->configs[win].pixel_formats = decon_formats;
633 		ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
634 		ctx->configs[win].zpos = win - ctx->first_win;
635 		ctx->configs[win].type = decon_win_types[win];
636 		ctx->configs[win].capabilities = capabilities[win];
638 		ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
639 					&ctx->configs[win]);
644 	exynos_plane = &ctx->planes[PRIMARY_WIN];
645 	out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
647 	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
648 			out_type, &decon_crtc_ops, ctx);
649 	if (IS_ERR(ctx->crtc))
650 		return PTR_ERR(ctx->crtc);
652 	decon_clear_channels(ctx->crtc);
654 	return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
659 	struct decon_context *ctx = dev_get_drvdata(dev);
661 	decon_atomic_disable(ctx->crtc);
664 	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
672 static void decon_handle_vblank(struct decon_context *ctx)
676 	spin_lock(&ctx->vblank_lock);
678 	frm = decon_get_frame_count(ctx, true);
680 	if (frm != ctx->frame_id) {
682 		if ((s32)(frm - ctx->frame_id) > 0)
683 			drm_crtc_handle_vblank(&ctx->crtc->base);
684 		ctx->frame_id = frm;
687 	spin_unlock(&ctx->vblank_lock);
692 	struct decon_context *ctx = dev_id;
695 	val = readl(ctx->addr + DECON_VIDINTCON1);
699 		writel(val, ctx->addr + DECON_VIDINTCON1);
700 		if (ctx->out_type & IFTYPE_HDMI) {
701 			val = readl(ctx->addr + DECON_VIDOUTCON0);
707 		decon_handle_vblank(ctx);
715 	struct decon_context *ctx = dev_get_drvdata(dev);
719 		clk_disable_unprepare(ctx->clks[i]);
726 	struct decon_context *ctx = dev_get_drvdata(dev);
730 		ret = clk_prepare_enable(ctx->clks[i]);
739 		clk_disable_unprepare(ctx->clks[i]);
761 static int decon_conf_irq(struct decon_context *ctx, const char *name,
764 	struct platform_device *pdev = to_platform_device(ctx->dev);
775 			dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
779 	ret = devm_request_irq(ctx->dev, irq, handler,
780 			       flags | IRQF_NO_AUTOEN, "drm_decon", ctx);
782 		dev_err(ctx->dev, "IRQ %s request failed\n", name);
792 	struct decon_context *ctx;
796 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
797 	if (!ctx)
800 	ctx->dev = dev;
801 	ctx->out_type = (unsigned long)of_device_get_match_data(dev);
802 	spin_lock_init(&ctx->vblank_lock);
804 	if (ctx->out_type & IFTYPE_HDMI)
805 		ctx->first_win = 1;
810 		clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
814 		ctx->clks[i] = clk;
817 	ctx->addr = devm_platform_ioremap_resource(pdev, 0);
818 	if (IS_ERR(ctx->addr))
819 		return PTR_ERR(ctx->addr);
821 	ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
824 	ctx->irq_vsync = ret;
826 	ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
829 	ctx->irq_lcd_sys = ret;
831 	ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
836 		ctx->te_irq = ret;
837 		ctx->out_type &= ~I80_HW_TRG;
840 	if (ctx->out_type & I80_HW_TRG) {
841 		ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
843 		if (IS_ERR(ctx->sysreg)) {
845 			return PTR_ERR(ctx->sysreg);
849 	platform_set_drvdata(pdev, ctx);