Lines Matching defs:val
179 #define etnaviv_field(val, field) \
180 (((val) & field##__MASK) >> field##__SHIFT)
769 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
770 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
771 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
1320 u32 val;
1323 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1324 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1325 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1328 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1329 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1330 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1340 u32 val;
1351 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1352 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1353 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1356 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1357 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1358 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);