gpu/drm/drm_mipi_dbi.c

104 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
108 	if (!dbi->read_commands)
112 		if (!dbi->read_commands[i])
114 		if (cmd == dbi->read_commands[i])
123  * @dbi: MIPI DBI structure
132 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
134 	if (!dbi->read_commands)
137 	if (!mipi_dbi_command_is_read(dbi, cmd))
140 	return mipi_dbi_command_buf(dbi, cmd, val, 1);
146  * @dbi: MIPI DBI structure
154 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
164 	mutex_lock(&dbi->cmdlock);
165 	ret = dbi->command(dbi, cmdbuf, data, len);
166 	mutex_unlock(&dbi->cmdlock);
175 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
185 	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
244 	struct mipi_dbi *dbi = &dbidev->dbi;
251 	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
253 	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
263 	struct mipi_dbi *dbi = &dbidev->dbi;
264 	bool swap = dbi->swap_bytes;
273 	if (!dbi->dc || !full || swap ||
286 	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
388 	struct mipi_dbi *dbi = &dbidev->dbi;
398 	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
597 	if (!dbidev->dbi.command)
674  * @dbi: MIPI DBI structure
678 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
680 	if (!dbi->reset)
683 	gpiod_set_value_cansleep(dbi->reset, 0);
685 	gpiod_set_value_cansleep(dbi->reset, 1);
692  * @dbi: MIPI DBI structure
702 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
706 	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
725 	struct mipi_dbi *dbi = &dbidev->dbi;
746 	if (cond && mipi_dbi_display_is_on(dbi))
749 	mipi_dbi_hw_reset(dbi);
750 	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
765 	if (dbi->reset)
854 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
859 	size_t chunk, max_chunk = dbi->tx_buf9_len;
860 	struct spi_device *spi = dbi->spi;
862 		.tx_buf = dbi->tx_buf9,
882 		dst = dbi->tx_buf9;
902 		dst = dbi->tx_buf9;
972 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
976 	struct spi_device *spi = dbi->spi;
988 		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
991 	max_chunk = dbi->tx_buf9_len;
992 	dst16 = dbi->tx_buf9;
1035 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
1038 	struct spi_device *spi = dbi->spi;
1045 			.tx_buf = dbi->tx_buf9,
1076 	dst16 = dbi->tx_buf9;
1088 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
1094 	if (mipi_dbi_command_is_read(dbi, *cmd))
1095 		return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1099 	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1103 	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1108 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1111 	struct spi_device *spi = dbi->spi;
1150 	gpiod_set_value_cansleep(dbi->dc, 0);
1175 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1178 	struct spi_device *spi = dbi->spi;
1183 	if (mipi_dbi_command_is_read(dbi, *cmd))
1184 		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1189 	gpiod_set_value_cansleep(dbi->dc, 0);
1196 	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1200 	gpiod_set_value_cansleep(dbi->dc, 1);
1211  * @dbi: MIPI DBI structure to initialize
1230 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1254 	dbi->spi = spi;
1255 	dbi->read_commands = mipi_dbi_dcs_read_commands;
1258 		dbi->command = mipi_dbi_typec3_command;
1259 		dbi->dc = dc;
1261 			dbi->swap_bytes = true;
1263 		dbi->command = mipi_dbi_typec1_command;
1264 		dbi->tx_buf9_len = SZ_16K;
1265 		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1266 		if (!dbi->tx_buf9)
1270 	mutex_init(&dbi->cmdlock);
1384 	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1397 	struct mipi_dbi *dbi = &dbidev->dbi;
1406 		if (!mipi_dbi_command_is_read(dbi, cmd))
1426 		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1469 	if (dbidev->dbi.read_commands)