drm/display/drm_dsc_helper.c

277  * @vdsc_cfg:
280 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
282 	if (!vdsc_cfg->rc_model_size)
283 		vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
284 	vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
285 	vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
286 	vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
288 	if (vdsc_cfg->bits_per_component <= 10)
289 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
291 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
305  * @vdsc_cfg: DSC Configuration data partially filled by driver
307 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
314 		     ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
317 		vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
323 	if (vdsc_cfg->bits_per_pixel == 6 << 4) {
324 		vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
325 		vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
1237  * @vdsc_cfg: DSC Configuration data partially filled by driver
1242 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type)
1248 	if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
1249 			 !vdsc_cfg->bits_per_component))
1270 				  vdsc_cfg->bits_per_pixel,
1271 				  vdsc_cfg->bits_per_component);
1275 	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
1276 	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
1277 	vdsc_cfg->initial_offset = rc_params->initial_offset;
1278 	vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
1279 	vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
1280 	vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
1281 	vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
1284 		vdsc_cfg->rc_range_params[i].range_min_qp =
1286 		vdsc_cfg->rc_range_params[i].range_max_qp =
1292 		vdsc_cfg->rc_range_params[i].range_bpg_offset =
1308  * @vdsc_cfg:
1311 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
1321 	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
1323 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
1327 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
1328 							  vdsc_cfg->bits_per_pixel,
1332 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
1336 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
1337 							  vdsc_cfg->bits_per_pixel,
1341 	if (vdsc_cfg->convert_rgb)
1342 		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
1343 					  (4 * vdsc_cfg->bits_per_component + 4)
1345 	else if (vdsc_cfg->native_422)
1346 		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
1347 			(4 * vdsc_cfg->bits_per_component + 4) +
1348 			3 * (4 * vdsc_cfg->bits_per_component) - 2;
1350 		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
1351 			(4 * vdsc_cfg->bits_per_component + 4) +
1352 			2 * (4 * vdsc_cfg->bits_per_component) - 2;
1354 	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
1357 	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
1360 	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
1361 		vdsc_cfg->initial_scale_value = groups_per_line + 8;
1364 	if (vdsc_cfg->initial_scale_value > 8)
1365 		vdsc_cfg->scale_decrement_interval = groups_per_line /
1366 			(vdsc_cfg->initial_scale_value - 8);
1368 		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
1370 	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
1371 		(vdsc_cfg->initial_xmit_delay *
1372 		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
1374 	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
1379 	final_scale = (vdsc_cfg->rc_model_size * 8) /
1380 		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
1381 	if (vdsc_cfg->slice_height > 1)
1387 		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
1388 							(vdsc_cfg->slice_height - 1));
1390 		vdsc_cfg->nfl_bpg_offset = 0;
1393 	groups_total = groups_per_line * vdsc_cfg->slice_height;
1396 	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
1397 						    vdsc_cfg->initial_offset +
1408 		vdsc_cfg->scale_increment_interval =
1409 				(vdsc_cfg->final_offset * (1 << 11)) /
1410 				((vdsc_cfg->nfl_bpg_offset +
1411 				vdsc_cfg->slice_bpg_offset) *
1418 		vdsc_cfg->scale_increment_interval = 0;
1426 	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
1427 		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
1428 			     vdsc_cfg->bits_per_pixel, 16) +
1429 		groups_per_line * vdsc_cfg->first_line_bpg_offset;
1431 	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
1432 	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
1433 	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
1441  * @vdsc_cfg: Pointer to DRM DSC config struct
1445 u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg)
1447 	WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
1448 	return vdsc_cfg->bits_per_pixel >> 4;