drm/display/drm_dp_helper.c

284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
300 			if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
326 		rd_interval = dpcd[offset];
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
342 	return __read_delay(aux, dpcd, dp_phy, uhbr, true);
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
349 	return __read_delay(aux, dpcd, dp_phy, uhbr, false);
374 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
376 	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
380 	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
398 					const u8 dpcd[DP_RECEIVER_CAP_SIZE])
401 					     dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
793  * @dpcd: DisplayPort configuration data
804 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
807 	return drm_dp_is_branch(dpcd) &&
808 		dpcd[DP_DPCD_REV] >= 0x11 &&
815  * @dpcd: DisplayPort configuration data
821 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
825 	if (dpcd[DP_DPCD_REV] < 0x11) {
826 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
908 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
910 	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
912 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
919 					  u8 dpcd[DP_RECEIVER_CAP_SIZE])
931 	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
942 	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
945 			    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
949 	if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
952 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
954 	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
963  * @dpcd: Buffer to store the resulting DPCD in
973 			  u8 dpcd[DP_RECEIVER_CAP_SIZE])
977 	ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
980 	if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
983 	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
987 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
996  * @dpcd: A cached copy of the port's DPCD
1007 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1016 	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
1023 	len = drm_dp_downstream_port_count(dpcd);
1027 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
1044  * @dpcd: DisplayPort configuration data
1050 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1053 	if (!drm_dp_is_branch(dpcd))
1056 	if (dpcd[DP_DPCD_REV] < 0x11)
1061 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1072  * @dpcd: DisplayPort configuration data
1079 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1083 	if (!drm_dp_is_branch(dpcd))
1086 	if (dpcd[DP_DPCD_REV] < 0x11) {
1087 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1121 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1125 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1137  * @dpcd: DisplayPort configuration data
1144 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1148 	if (!drm_dp_is_branch(dpcd))
1151 	if (dpcd[DP_DPCD_REV] < 0x11) {
1152 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1181  * @dpcd: DisplayPort configuration data
1187 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1191 	if (!drm_dp_is_branch(dpcd))
1194 	if (dpcd[DP_DPCD_REV] < 0x11) {
1195 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1213 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1238  * @dpcd: DisplayPort configuration data
1243 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1246 	if (!drm_dp_is_branch(dpcd))
1249 	if (dpcd[DP_DPCD_REV] < 0x13)
1256 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1269  * @dpcd: DisplayPort configuration data
1274 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1277 	if (!drm_dp_is_branch(dpcd))
1280 	if (dpcd[DP_DPCD_REV] < 0x13)
1285 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1298  * @dpcd: DisplayPort configuration data
1305 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1309 	if (!drm_dp_is_branch(dpcd))
1312 	if (dpcd[DP_DPCD_REV] < 0x13)
1317 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1330  * @dpcd: DisplayPort configuration data
1339 		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1345 	if (!drm_dp_is_branch(dpcd))
1348 	if (dpcd[DP_DPCD_REV] < 0x11)
1398  * @dpcd: DisplayPort configuration data
1405 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1410 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1418 	bool branch_device = drm_dp_is_branch(dpcd);
1466 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1470 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1474 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1478 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1488  * @dpcd: DisplayPort configuration data
1492 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1496 	if (!drm_dp_is_branch(dpcd))
1499 	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1500 		type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1542  * @dpcd: DisplayPort configuration data
1549 				      const u8 *dpcd,
1555 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1566  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1575 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1580 		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1581 		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2536 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2544 	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2564  * @dpcd: DisplayPort configuration data
2572 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2575 	return drm_dp_read_lttpr_regs(aux, dpcd,
2584  * @dpcd: DisplayPort configuration data
2593 			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2597 	return drm_dp_read_lttpr_regs(aux, dpcd,
2968  * @dpcd: DisplayPort configuration data
2972 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
2976 	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
2993  * @dpcd: DisplayPort configuration data
2997 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3001 	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3089  * @dpcd: DisplayPort configuration data
3095 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],