Lines Matching defs:refclk
375 struct clk *refclk;
574 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
580 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
595 * refclk * mul / (ext_pre_div * pre_div) should be in range:
608 refclk);
613 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
614 * We don't allow any refclk > 200 MHz, only check lower bounds.
616 if (refclk / ext_div[i_pre] < 1000000)
624 iclk = refclk / (div * ext_div[i_pre]);
630 do_div(tmp, refclk);
637 clk = (refclk / ext_div[i_pre] / div) * mul;
663 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
667 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
726 rate = clk_get_rate(tc->refclk);
741 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
1412 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1456 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
2335 tc->refclk = devm_clk_get_enabled(dev, "ref");
2336 if (IS_ERR(tc->refclk))
2337 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2432 clk_get_rate(tc->refclk) * 2 / 1000);