Lines Matching refs:nwl_dsi_write

136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
224 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
225 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
244 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
245 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
246 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
247 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
290 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
291 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
296 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
298 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
305 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
306 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
311 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
312 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
316 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
317 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
318 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
320 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
321 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
322 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
323 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
325 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
326 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
327 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
328 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
341 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
520 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
536 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
559 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
562 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);