bridge/imx/imx8qxp-pixel-combiner.c

64 	struct imx8qxp_pc *pc;
76 static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset)
78 	return readl(pc->base + offset);
82 imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
84 	writel(value, pc->base + offset);
88 imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
90 	imx8qxp_pc_write(pc, offset + PC_REG_SET, value);
94 imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
96 	imx8qxp_pc_write(pc, offset + PC_REG_CLR, value);
114 	struct imx8qxp_pc *pc = ch->pc;
117 		DRM_DEV_ERROR(pc->dev,
123 		DRM_DEV_ERROR(pc->dev, "missing encoder\n");
138 	struct imx8qxp_pc *pc = ch->pc;
142 	ret = pm_runtime_get_sync(pc->dev);
144 		DRM_DEV_ERROR(pc->dev,
147 	ret = clk_prepare_enable(pc->clk_apb);
149 		DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
153 	imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
157 	imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
161 	imx8qxp_pc_write_set(pc, PC_CTRL_REG,
165 	imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE);
168 	val = imx8qxp_pc_read(pc, PC_CTRL_REG);
176 	imx8qxp_pc_write(pc, PC_CTRL_REG, val);
179 	imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id));
181 	clk_disable_unprepare(pc->clk_apb);
189 	struct imx8qxp_pc *pc = ch->pc;
192 	ret = pm_runtime_put(pc->dev);
194 		DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret);
277 	struct imx8qxp_pc *pc;
285 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
286 	if (!pc)
289 	pc->base = devm_platform_ioremap_resource(pdev, 0);
290 	if (IS_ERR(pc->base))
291 		return PTR_ERR(pc->base);
293 	pc->dev = dev;
295 	pc->clk_apb = devm_clk_get(dev, "apb");
296 	if (IS_ERR(pc->clk_apb)) {
297 		ret = PTR_ERR(pc->clk_apb);
303 	platform_set_drvdata(pdev, pc);
315 		ch = &pc->ch[i];
316 		ch->pc = pc;
353 	if (i == 1 && pc->ch[0].next_bridge)
354 		drm_bridge_remove(&pc->ch[0].bridge);
362 	struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
367 		ch = &pc->ch[i];
382 	struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
385 	ret = clk_prepare_enable(pc->clk_apb);
387 		DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
391 	imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
393 	clk_disable_unprepare(pc->clk_apb);
404 	struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
407 	ret = clk_prepare_enable(pc->clk_apb);
409 		DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
415 	imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
417 	clk_disable_unprepare(pc->clk_apb);