Lines Matching refs:ctx
46 static int i2c_access_workaround(struct anx7625_data *ctx,
53 if (client == ctx->last_client)
56 ctx->last_client = client;
58 if (client == ctx->i2c.tcpc_client)
60 else if (client == ctx->i2c.tx_p0_client)
62 else if (client == ctx->i2c.tx_p1_client)
64 else if (client == ctx->i2c.rx_p0_client)
66 else if (client == ctx->i2c.rx_p1_client)
80 static int anx7625_reg_read(struct anx7625_data *ctx,
86 i2c_access_workaround(ctx, client);
96 static int anx7625_reg_block_read(struct anx7625_data *ctx,
103 i2c_access_workaround(ctx, client);
113 static int anx7625_reg_write(struct anx7625_data *ctx,
120 i2c_access_workaround(ctx, client);
131 static int anx7625_reg_block_write(struct anx7625_data *ctx,
138 i2c_access_workaround(ctx, client);
148 static int anx7625_write_or(struct anx7625_data *ctx,
154 val = anx7625_reg_read(ctx, client, offset);
158 return anx7625_reg_write(ctx, client, offset, (val | (mask)));
161 static int anx7625_write_and(struct anx7625_data *ctx,
167 val = anx7625_reg_read(ctx, client, offset);
171 return anx7625_reg_write(ctx, client, offset, (val & (mask)));
174 static int anx7625_write_and_or(struct anx7625_data *ctx,
180 val = anx7625_reg_read(ctx, client, offset);
184 return anx7625_reg_write(ctx, client,
188 static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
192 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
195 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
202 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
204 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
207 static int wait_aux_op_finish(struct anx7625_data *ctx)
209 struct device *dev = ctx->dev;
214 ctx, val,
223 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
233 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
236 struct device *dev = ctx->dev;
259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
282 ret = wait_aux_op_finish(ctx);
293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
303 static int anx7625_video_mute_control(struct anx7625_data *ctx,
310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
425 static int anx7625_odfc_config(struct anx7625_data *ctx,
429 struct device *dev = ctx->dev;
432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
465 static int anx7625_set_k_value(struct anx7625_data *ctx)
467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
473 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
477 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
479 struct device *dev = ctx->dev;
485 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
497 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
498 (ctx->dt.pixelclock.min / 1000) & 0xFF);
499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
500 (ctx->dt.pixelclock.min / 1000) >> 8);
502 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
504 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
505 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
510 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
515 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
516 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
521 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
524 ctx->dt.hfront_porch.min >> 8);
526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
527 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
532 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
536 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
537 ctx->dt.vactive.min);
538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
539 ctx->dt.vactive.min >> 8);
541 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
542 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
545 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
548 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
564 anx7625_set_k_value(ctx);
566 ret |= anx7625_odfc_config(ctx, post_divider - 1);
574 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
577 struct device *dev = ctx->dev;
580 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
587 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
590 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
594 struct device *dev = ctx->dev;
597 ret = anx7625_swap_dsi_lane3(ctx);
612 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
626 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
629 ret |= anx7625_dsi_video_timing_config(ctx);
636 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
639 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
643 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
646 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
657 static int anx7625_dsi_config(struct anx7625_data *ctx)
659 struct device *dev = ctx->dev;
665 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
668 ret |= anx7625_api_dsi_config(ctx);
676 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
679 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
689 static int anx7625_api_dpi_config(struct anx7625_data *ctx)
691 struct device *dev = ctx->dev;
692 u16 freq = ctx->dt.pixelclock.min / 1000;
696 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
698 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
703 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
706 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
712 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
720 static int anx7625_dpi_config(struct anx7625_data *ctx)
722 struct device *dev = ctx->dev;
728 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
735 ret = anx7625_config_bit_matrix(ctx);
741 ret = anx7625_api_dpi_config(ctx);
748 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
751 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
759 static int anx7625_read_flash_status(struct anx7625_data *ctx)
761 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
764 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
767 struct device *dev = ctx->dev;
770 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
772 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
779 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
781 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
788 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
791 ctx, val,
800 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
814 static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
817 struct device *dev = ctx->dev;
820 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
822 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
831 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
836 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
842 static int anx7625_hdcp_disable(struct anx7625_data *ctx)
845 struct device *dev = ctx->dev;
850 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
852 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
858 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
862 static int anx7625_hdcp_enable(struct anx7625_data *ctx)
866 struct device *dev = ctx->dev;
868 ret = anx7625_hdcp_key_probe(ctx);
875 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap);
887 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
892 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
897 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
900 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
902 ret |= anx7625_hdcp_key_load(ctx);
908 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
911 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
917 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
921 static void anx7625_dp_start(struct anx7625_data *ctx)
924 struct device *dev = ctx->dev;
927 if (!ctx->display_timing_valid) {
935 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
940 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
942 if (ctx->pdata.is_dpi)
943 ret = anx7625_dpi_config(ctx);
945 ret = anx7625_dsi_config(ctx);
950 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
952 ctx->dp_en = 1;
955 static void anx7625_dp_stop(struct anx7625_data *ctx)
957 struct device *dev = ctx->dev;
967 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
968 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
970 ret |= anx7625_video_mute_control(ctx, 1);
975 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
979 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
981 ctx->dp_en = 0;
984 static int sp_tx_rst_aux(struct anx7625_data *ctx)
988 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
990 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
995 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
999 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1001 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1003 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1005 return (ret | wait_aux_op_finish(ctx));
1008 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1012 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1014 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1016 return (ret | wait_aux_op_finish(ctx));
1019 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1022 struct device *dev = ctx->dev;
1024 sp_tx_aux_wr(ctx, 0x7e);
1025 sp_tx_aux_rd(ctx, 0x01);
1026 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1040 static int edid_read(struct anx7625_data *ctx,
1044 struct device *dev = ctx->dev;
1047 sp_tx_aux_wr(ctx, offset);
1049 ret = sp_tx_aux_rd(ctx, 0xf1);
1052 ret = sp_tx_rst_aux(ctx);
1055 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1070 static int segments_edid_read(struct anx7625_data *ctx,
1075 struct device *dev = ctx->dev;
1078 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1080 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1086 ret |= wait_aux_op_finish(ctx);
1088 ret |= sp_tx_aux_wr(ctx, segment);
1090 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1098 sp_tx_aux_wr(ctx, offset);
1100 ret = sp_tx_aux_rd(ctx, 0xf1);
1103 ret = sp_tx_rst_aux(ctx);
1106 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1120 static int sp_tx_edid_read(struct anx7625_data *ctx,
1130 struct device *dev = ctx->dev;
1133 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1135 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1137 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1144 blocks_num = sp_tx_get_edid_block(ctx);
1156 g_edid_break = edid_read(ctx, offset,
1178 ret = segments_edid_read(ctx, count / 2,
1199 ret = segments_edid_read(ctx, count / 2,
1226 ret = sp_tx_rst_aux(ctx);
1235 static void anx7625_power_on(struct anx7625_data *ctx)
1237 struct device *dev = ctx->dev;
1240 if (!ctx->pdata.low_power_mode) {
1245 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1246 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1258 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1261 gpiod_set_value(ctx->pdata.gpio_reset, 1);
1268 regulator_disable(ctx->pdata.supplies[i].consumer);
1271 static void anx7625_power_standby(struct anx7625_data *ctx)
1273 struct device *dev = ctx->dev;
1276 if (!ctx->pdata.low_power_mode) {
1281 gpiod_set_value(ctx->pdata.gpio_reset, 0);
1283 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1286 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1287 ctx->pdata.supplies);
1295 static void anx7625_config(struct anx7625_data *ctx)
1297 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1301 static int anx7625_hpd_timer_config(struct anx7625_data *ctx)
1306 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1308 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1311 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1318 static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx)
1320 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2);
1323 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1325 struct device *dev = ctx->dev;
1329 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1331 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1334 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1347 ctx, val,
1352 anx7625_hpd_timer_config(ctx);
1355 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1358 struct device *dev = ctx->dev;
1361 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1370 anx7625_disable_pd_protocol(ctx);
1373 anx7625_reg_read(ctx,
1374 ctx->i2c.rx_p0_client,
1376 anx7625_reg_read(ctx,
1377 ctx->i2c.rx_p0_client,
1385 static void anx7625_power_on_init(struct anx7625_data *ctx)
1390 anx7625_power_on(ctx);
1391 anx7625_config(ctx);
1394 if (!anx7625_ocm_loading_check(ctx))
1398 anx7625_power_standby(ctx);
1435 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1437 ctx->hpd_status = 0;
1438 ctx->hpd_high_cnt = 0;
1441 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1444 struct device *dev = ctx->dev;
1446 if (ctx->hpd_high_cnt >= 2) {
1451 ctx->hpd_status = 1;
1452 ctx->hpd_high_cnt++;
1455 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1458 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1460 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1466 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1473 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1475 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1478 static int _anx7625_hpd_polling(struct anx7625_data *ctx,
1482 struct device *dev = ctx->dev;
1485 if (ctx->pdata.intp_irq)
1489 ctx, val,
1499 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1501 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1504 anx7625_start_dp_work(ctx);
1506 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1507 drm_helper_hpd_irq_event(ctx->bridge.dev);
1515 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1516 struct device *dev = ctx->dev;
1520 ret = _anx7625_hpd_polling(ctx, wait_us);
1527 static void anx7625_remove_edid(struct anx7625_data *ctx)
1529 ctx->slimport_edid_p.edid_block_num = -1;
1532 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1536 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1537 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1539 ctx->pdata.lane0_reg_data[i]);
1541 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1542 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1544 ctx->pdata.lane1_reg_data[i]);
1547 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1549 struct device *dev = ctx->dev;
1557 anx7625_remove_edid(ctx);
1558 anx7625_stop_dp_work(ctx);
1561 anx7625_start_dp_work(ctx);
1562 anx7625_dp_adjust_swing(ctx);
1566 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1569 struct device *dev = ctx->dev;
1571 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1578 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1585 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1596 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1604 dp_hpd_change_handler(ctx, status & HPD_STATUS);
1612 struct anx7625_data *ctx = container_of(work,
1615 mutex_lock(&ctx->lock);
1617 if (pm_runtime_suspended(ctx->dev)) {
1618 mutex_unlock(&ctx->lock);
1622 event = anx7625_hpd_change_detect(ctx);
1624 mutex_unlock(&ctx->lock);
1629 if (ctx->bridge_attached)
1630 drm_helper_hpd_irq_event(ctx->bridge.dev);
1635 struct anx7625_data *ctx = (struct anx7625_data *)data;
1637 queue_work(ctx->workqueue, &ctx->work);
1760 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1761 struct device *dev = ctx->dev;
1765 mutex_lock(&ctx->aux_lock);
1778 ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1782 mutex_unlock(&ctx->aux_lock);
1787 static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx)
1789 struct device *dev = ctx->dev;
1790 struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1793 if (ctx->slimport_edid_p.edid_block_num > 0)
1797 _anx7625_hpd_polling(ctx, 5000 * 100);
1798 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);
1809 return drm_edid_alloc(ctx->slimport_edid_p.edid_raw_data,
1813 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1815 struct device *dev = ctx->dev;
1819 if (ctx->pdata.panel_bridge)
1822 return ctx->hpd_status ? connector_status_connected :
1830 struct anx7625_data *ctx = dev_get_drvdata(dev);
1834 if (anx7625_sink_detect(ctx) == connector_status_disconnected) {
1849 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1854 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1878 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1901 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1904 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1907 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1938 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1941 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1975 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1978 if (ctx->plugged_cb && ctx->codec_dev) {
1979 ctx->plugged_cb(ctx->codec_dev,
1988 struct anx7625_data *ctx = data;
1990 ctx->plugged_cb = fn;
1991 ctx->codec_dev = codec_dev;
1992 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx));
2000 struct anx7625_data *ctx = dev_get_drvdata(dev);
2002 if (!ctx->connector) {
2007 memcpy(buf, ctx->connector->eld,
2008 min(sizeof(ctx->connector->eld), len));
2022 static void anx7625_unregister_audio(struct anx7625_data *ctx)
2024 struct device *dev = ctx->dev;
2026 if (ctx->audio_pdev) {
2027 platform_device_unregister(ctx->audio_pdev);
2028 ctx->audio_pdev = NULL;
2034 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
2040 .data = ctx,
2043 ctx->audio_pdev = platform_device_register_data(dev,
2049 if (IS_ERR(ctx->audio_pdev))
2050 return PTR_ERR(ctx->audio_pdev);
2057 static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
2060 struct device *dev = ctx->dev;
2068 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2080 dsi->lanes = ctx->pdata.mipi_lanes;
2087 ctx->dsi = dsi;
2092 static int anx7625_attach_dsi(struct anx7625_data *ctx)
2094 struct device *dev = ctx->dev;
2099 ret = devm_mipi_dsi_attach(dev, ctx->dsi);
2114 struct anx7625_data *ctx;
2119 ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2120 dev = ctx->dev;
2122 if (!ctx->connector) {
2127 drm_dev = ctx->connector->dev;
2129 mutex_lock(&ctx->hdcp_wq_lock);
2131 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2134 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2135 drm_hdcp_update_content_protection(ctx->connector,
2136 ctx->hdcp_cp);
2140 mutex_unlock(&ctx->hdcp_wq_lock);
2144 static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2147 struct device *dev = ctx->dev;
2153 if (cp == ctx->hdcp_cp)
2157 if (ctx->dp_en) {
2159 anx7625_hdcp_enable(ctx);
2161 queue_delayed_work(ctx->hdcp_workqueue,
2162 &ctx->hdcp_work,
2168 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2172 anx7625_hdcp_disable(ctx);
2173 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2174 drm_hdcp_update_content_protection(ctx->connector,
2175 ctx->hdcp_cp);
2190 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2192 struct device *dev = ctx->dev;
2203 ctx->aux.drm_dev = bridge->dev;
2204 err = drm_dp_aux_register(&ctx->aux);
2210 if (ctx->pdata.panel_bridge) {
2212 ctx->pdata.panel_bridge,
2213 &ctx->bridge, flags);
2218 ctx->bridge_attached = 1;
2225 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2227 drm_dp_aux_unregister(&ctx->aux);
2235 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2236 struct device *dev = ctx->dev;
2256 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2257 struct device *dev = ctx->dev;
2261 ctx->dt.pixelclock.min = mode->clock;
2262 ctx->dt.hactive.min = mode->hdisplay;
2263 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2264 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2265 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2266 ctx->dt.vactive.min = mode->vdisplay;
2267 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2268 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2269 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2271 ctx->display_timing_valid = 1;
2273 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2275 ctx->dt.hactive.min,
2276 ctx->dt.hsync_len.min,
2277 ctx->dt.hfront_porch.min,
2278 ctx->dt.hback_porch.min);
2280 ctx->dt.vactive.min,
2281 ctx->dt.vsync_len.min,
2282 ctx->dt.vfront_porch.min,
2283 ctx->dt.vback_porch.min);
2302 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2303 struct device *dev = ctx->dev;
2311 if (!ctx->pdata.panel_bridge)
2420 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2421 struct device *dev = ctx->dev;
2428 return anx7625_connector_atomic_check(ctx, conn_state);
2434 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2435 struct device *dev = ctx->dev;
2450 ctx->connector = connector;
2453 _anx7625_hpd_polling(ctx, 5000 * 100);
2455 anx7625_dp_start(ctx);
2461 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2462 struct device *dev = ctx->dev;
2466 ctx->connector = NULL;
2467 anx7625_dp_stop(ctx);
2469 mutex_lock(&ctx->aux_lock);
2471 mutex_unlock(&ctx->aux_lock);
2477 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2478 struct device *dev = ctx->dev;
2482 return anx7625_sink_detect(ctx);
2488 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2489 struct device *dev = ctx->dev;
2493 return anx7625_edid_read(ctx);
2511 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2514 struct device *dev = ctx->dev;
2516 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2518 if (IS_ERR(ctx->i2c.tx_p0_client))
2519 return PTR_ERR(ctx->i2c.tx_p0_client);
2521 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2523 if (IS_ERR(ctx->i2c.tx_p1_client))
2524 return PTR_ERR(ctx->i2c.tx_p1_client);
2526 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2528 if (IS_ERR(ctx->i2c.tx_p2_client))
2529 return PTR_ERR(ctx->i2c.tx_p2_client);
2531 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2533 if (IS_ERR(ctx->i2c.rx_p0_client))
2534 return PTR_ERR(ctx->i2c.rx_p0_client);
2536 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2538 if (IS_ERR(ctx->i2c.rx_p1_client))
2539 return PTR_ERR(ctx->i2c.rx_p1_client);
2541 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2543 if (IS_ERR(ctx->i2c.rx_p2_client))
2544 return PTR_ERR(ctx->i2c.rx_p2_client);
2546 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter,
2548 if (IS_ERR(ctx->i2c.tcpc_client))
2549 return PTR_ERR(ctx->i2c.tcpc_client);
2556 struct anx7625_data *ctx = dev_get_drvdata(dev);
2558 mutex_lock(&ctx->lock);
2560 anx7625_stop_dp_work(ctx);
2561 anx7625_power_standby(ctx);
2563 mutex_unlock(&ctx->lock);
2570 struct anx7625_data *ctx = dev_get_drvdata(dev);
2572 mutex_lock(&ctx->lock);
2574 anx7625_power_on_init(ctx);
2576 mutex_unlock(&ctx->lock);