bridge/analogix/analogix_dp_reg.c

26 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
31 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
33 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
35 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
37 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
41 void analogix_dp_stop_video(struct analogix_dp_device *dp)
45 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
47 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
50 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
61 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
64 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
69 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
72 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
74 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
76 		if (dp->plat_data->dev_type == RK3288_DP)
79 		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
80 		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
81 		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
82 		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
83 		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
87 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
91 	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
95 	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
98 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
101 	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
104 	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
105 	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
106 	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
107 	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
108 	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
111 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
112 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
113 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
114 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
115 	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
118 void analogix_dp_reset(struct analogix_dp_device *dp)
122 	analogix_dp_stop_video(dp);
123 	analogix_dp_enable_video_mute(dp, 0);
125 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
133 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
138 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
142 	analogix_dp_lane_swap(dp, 0);
144 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
145 	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
146 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
147 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
149 	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
150 	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
152 	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
153 	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
155 	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
157 	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
159 	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
160 	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
162 	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
163 	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
165 	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
168 void analogix_dp_swreset(struct analogix_dp_device *dp)
170 	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
173 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
179 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
182 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
185 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
188 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
191 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
194 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
199 	reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
201 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
203 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
205 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
208 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
214 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
217 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
220 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
224 	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
231 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
237 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
242 	reg = readl(dp->reg_base + pd_addr);
247 	writel(reg, dp->reg_base + pd_addr);
250 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
258 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
263 		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
268 		reg = readl(dp->reg_base + phy_pd_addr);
273 		writel(reg, dp->reg_base + phy_pd_addr);
277 		reg = readl(dp->reg_base + phy_pd_addr);
283 		writel(reg, dp->reg_base + phy_pd_addr);
287 		reg = readl(dp->reg_base + phy_pd_addr);
293 		writel(reg, dp->reg_base + phy_pd_addr);
297 		reg = readl(dp->reg_base + phy_pd_addr);
303 		writel(reg, dp->reg_base + phy_pd_addr);
307 		reg = readl(dp->reg_base + phy_pd_addr);
313 		writel(reg, dp->reg_base + phy_pd_addr);
321 		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
326 		reg = readl(dp->reg_base + phy_pd_addr);
332 		writel(reg, dp->reg_base + phy_pd_addr);
333 		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
339 			writel(reg, dp->reg_base + phy_pd_addr);
342 			writel(reg, dp->reg_base + phy_pd_addr);
345 			writel(reg, dp->reg_base + phy_pd_addr);
348 			writel(0x00, dp->reg_base + phy_pd_addr);
356 int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
361 	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
364 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
366 	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
368 	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
371 	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
372 		analogix_dp_set_pll_power_down(dp, 0);
374 		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
377 				dev_err(dp->dev, "failed to get pll lock status\n");
385 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
388 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
392 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
396 	if (dp->hpd_gpiod)
400 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
403 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
406 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
410 	if (dp->hpd_gpiod)
413 	analogix_dp_clear_hotplug_interrupts(dp);
415 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
417 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
420 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
424 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
426 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
429 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
433 	if (dp->hpd_gpiod) {
434 		reg = gpiod_get_value(dp->hpd_gpiod);
441 		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
456 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
461 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
463 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
466 void analogix_dp_init_aux(struct analogix_dp_device *dp)
472 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
474 	analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true);
476 	analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false);
478 	analogix_dp_reset_aux(dp);
481 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
490 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
494 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
497 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
499 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
502 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
506 	if (dp->hpd_gpiod) {
507 		if (gpiod_get_value(dp->hpd_gpiod))
510 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
518 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
522 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
524 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
527 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
533 		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
536 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
540 	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
544 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
549 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
552 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
556 	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
560 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
566 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
568 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
570 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
572 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
576 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
584 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
588 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
592 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
596 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
602 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
609 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
614 	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
617 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
620 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
625 	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
628 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
631 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
636 	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
639 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
642 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
647 	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
650 	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
653 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
659 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
662 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
668 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
671 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
677 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
680 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
686 	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
689 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
691 	return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
694 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
696 	return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
699 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
701 	return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
704 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
706 	return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
709 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
713 	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
715 	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
721 	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
724 void analogix_dp_init_video(struct analogix_dp_device *dp)
729 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
732 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
735 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
738 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
741 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
744 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
749 	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
750 		(dp->video_info.color_depth << IN_BPC_SHIFT) |
751 		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
752 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
755 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
757 	if (dp->video_info.ycbcr_coeff)
761 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
764 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
768 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
769 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
771 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
774 		dev_dbg(dp->dev, "Input stream clock not detected.\n");
778 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
779 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
781 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
782 	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
785 		dev_dbg(dp->dev, "Input stream clk is changing\n");
792 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
799 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
801 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
803 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
805 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
807 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
810 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
812 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
814 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
816 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
818 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
820 		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
821 		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
822 		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
826 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
831 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
833 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
835 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
837 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
841 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
846 		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
849 		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
851 		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
854 		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
858 void analogix_dp_start_video(struct analogix_dp_device *dp)
862 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
864 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
867 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
871 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
872 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
874 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
876 		dev_dbg(dp->dev, "Input video stream is not detected.\n");
883 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
887 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
888 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
894 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
896 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
898 	reg |= (dp->video_info.interlaced << 2);
899 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
901 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
903 	reg |= (dp->video_info.v_sync_polarity << 1);
904 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
906 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
908 	reg |= (dp->video_info.h_sync_polarity << 0);
909 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
912 	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
915 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
919 	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
921 	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
924 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
928 	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
930 	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
933 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
935 	writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
938 static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp)
943 	val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
945 		dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val);
951 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
959 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
961 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
965 	       dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL);
968 	writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0);
969 	writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1);
970 	writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2);
971 	writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3);
974 	writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
975 	writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
976 	writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
977 	writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
980 	writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
981 	writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
984 	val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
986 	writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
989 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
991 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
994 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
996 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1010 	ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
1017 		dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
1023 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
1039 	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
1067 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
1071 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
1073 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
1075 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
1080 			writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1093 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
1095 	ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2,
1098 		dev_err(dp->dev, "AUX CH enable timeout!\n");
1104 	ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA,
1107 		dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
1112 	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
1115 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1116 	status_reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
1118 		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
1120 		dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n",
1127 			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1135 	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
1151 	analogix_dp_init_aux(dp);