bridge/analogix/analogix_dp_core.c

239 				       int pre_emphasis, int lane)
241 	switch (lane) {
262 	int lane, lane_count, pll_tries, retval;
269 	for (lane = 0; lane < lane_count; lane++)
270 		dp->link_train.cr_loop[lane] = 0;
290 	for (lane = 0; lane < lane_count; lane++)
292 			PRE_EMPHASIS_LEVEL_0, lane);
316 	for (lane = 0; lane < lane_count; lane++)
317 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
328 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
330 	int shift = (lane & 1) * 4;
331 	u8 link_value = link_status[lane >> 1];
338 	int lane;
341 	for (lane = 0; lane < lane_count; lane++) {
342 		lane_status = analogix_dp_get_lane_status(link_status, lane);
352 	int lane;
358 	for (lane = 0; lane < lane_count; lane++) {
359 		lane_status = analogix_dp_get_lane_status(link_status, lane);
369 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
371 	int shift = (lane & 1) * 4;
372 	u8 link_value = adjust_request[lane >> 1];
379 					int lane)
381 	int shift = (lane & 1) * 4;
382 	u8 link_value = adjust_request[lane >> 1];
388 					       u8 training_lane_set, int lane)
390 	switch (lane) {
410 				   int lane)
414 	switch (lane) {
446 	int lane, lane_count;
450 	for (lane = 0; lane < lane_count; lane++) {
452 						adjust_request, lane);
454 						adjust_request, lane);
463 		dp->link_train.training_lane[lane] = training_lane;
469 	int lane, lane_count, retval;
499 		for (lane = 0; lane < lane_count; lane++) {
501 							dp, lane);
503 							adjust_request, lane);
505 							adjust_request, lane);
511 				dp->link_train.cr_loop[lane]++;
513 			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
517 					dp->link_train.cr_loop[lane],
527 	for (lane = 0; lane < lane_count; lane++)
529 			dp->link_train.training_lane[lane], lane);
541 	int lane, lane_count, retval;
584 		dev_dbg(dp->dev, "final lane count = %.2x\n",
601 	for (lane = 0; lane < lane_count; lane++)
603 			dp->link_train.training_lane[lane], lane);
635 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
671 	/* Setup TX lane count & rate */
1644 		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1656 		of_property_read_u32(dp_node, "samsung,lane-count",