bridge/analogix/analogix_dp_core.c

262 	int lane, lane_count, pll_tries, retval;
279 	retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
280 	if (retval < 0)
281 		return retval;
283 	retval = analogix_dp_set_enhanced_mode(dp);
284 	if (retval < 0) {
286 		return retval;
310 	retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
313 	if (retval < 0)
314 		return retval;
320 	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
322 	if (retval < 0)
323 		return retval;
469 	int lane, lane_count, retval;
477 	retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
478 	if (retval < 0)
479 		return retval;
481 	retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
483 	if (retval < 0)
484 		return retval;
490 		retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
493 		if (retval < 0)
494 			return retval;
531 	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
533 	if (retval < 0)
534 		return retval;
541 	int lane, lane_count, retval;
549 	retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
550 	if (retval < 0)
551 		return retval;
558 	retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
560 	if (retval < 0)
561 		return retval;
563 	retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
565 	if (retval < 0)
566 		return retval;
572 		retval = analogix_dp_training_pattern_dis(dp);
573 		if (retval < 0)
574 			return retval;
605 	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
607 	if (retval < 0)
608 		return retval;
644 	int retval = 0;
683 	while (!retval && !training_finished) {
686 			retval = analogix_dp_link_start(dp);
687 			if (retval)
691 			retval = analogix_dp_process_clock_recovery(dp);
692 			if (retval)
696 			retval = analogix_dp_process_equalizer_training(dp);
697 			if (retval)
707 	if (retval)
708 		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
710 	return retval;