Lines Matching refs:err
9 #include <linux/err.h>
117 int err;
119 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
121 if (err)
122 return err;
124 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
126 if (err)
127 return err;
134 int err;
136 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
138 if (err)
139 return err;
141 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
143 if (err)
144 return err;
161 int err;
163 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
165 if (err)
166 return err;
168 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
171 if (err)
172 return err;
174 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
177 if (err)
178 return err;
180 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
183 if (err)
184 return err;
187 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
190 if (err)
191 return err;
193 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
196 if (err)
197 return err;
199 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
201 if (err)
202 return err;
204 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
206 if (err)
207 return err;
209 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
211 if (err)
212 return err;
215 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
217 if (err)
218 return err;
221 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
224 if (err)
225 return err;
227 err = anx78xx_clear_hpd(anx78xx);
228 if (err)
229 return err;
242 int err;
248 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
250 if (err)
251 return err;
256 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
261 if (err)
262 return err;
270 int err;
272 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
276 if (err)
277 return err;
279 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
281 if (err)
282 return err;
284 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
286 if (err)
287 return err;
289 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
291 if (err)
292 return err;
294 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
297 if (err)
298 return err;
300 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
302 if (err)
303 return err;
305 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
308 if (err)
309 return err;
311 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
315 if (err)
316 return err;
329 int err;
332 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
334 if (err)
335 return err;
338 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
340 if (err)
341 return err;
343 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
346 if (err)
347 return err;
349 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
352 if (err)
353 return err;
355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
357 if (err)
358 return err;
360 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
362 if (err)
363 return err;
369 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
371 if (err)
372 return err;
374 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
376 if (err)
377 return err;
379 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
381 if (err)
382 return err;
384 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
386 if (err)
387 return err;
389 err = anx78xx_xtal_clk_sel(anx78xx);
390 if (err)
391 return err;
393 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
395 if (err)
396 return err;
398 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
401 if (err)
402 return err;
408 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
410 if (err)
411 return err;
413 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
415 if (err)
416 return err;
419 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
421 if (err)
422 return err;
424 err = anx78xx_link_phy_initialization(anx78xx);
425 if (err)
426 return err;
429 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
431 if (err)
432 return err;
439 int err;
445 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
446 if (err)
447 return err;
449 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
451 if (err)
452 return err;
454 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
456 if (err)
457 return err;
459 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
461 if (err)
462 return err;
470 int err;
476 err = regulator_enable(pdata->dvdd10);
477 if (err) {
479 err);
506 int err;
518 err = regulator_disable(pdata->dvdd10);
519 if (err) {
521 err);
533 int err;
536 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
541 err = anx78xx_enable_interrupts(anx78xx);
542 if (err) {
543 DRM_ERROR("Failed to enable interrupts: %d\n", err);
547 err = anx78xx_rx_initialization(anx78xx);
548 if (err) {
549 DRM_ERROR("Failed receiver initialization: %d\n", err);
553 err = anx78xx_tx_initialization(anx78xx);
554 if (err) {
555 DRM_ERROR("Failed transmitter initialization: %d\n", err);
568 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
571 return err;
607 int err;
609 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
611 if (err)
612 return err;
614 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
617 if (err)
618 return err;
620 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
621 if (err < 0)
622 return err;
635 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
637 if (err)
638 return err;
640 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
642 if (err)
643 return err;
646 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
648 if (err < 0) {
649 DRM_ERROR("Failed to read DPCD: %d\n", err);
650 return err;
654 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
656 if (err)
657 return err;
664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);
665 if (err < 0) {
667 err);
668 return err;
674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);
675 if (err < 0) {
677 err);
678 return err;
690 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
692 if (err)
693 return err;
698 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
700 if (err)
701 return err;
703 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
705 if (err < 0)
706 return err;
708 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
709 if (err < 0)
710 return err;
715 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
719 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
722 if (err)
723 return err;
725 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
728 if (err)
729 return err;
736 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,
738 if (err < 0) {
739 DRM_ERROR("Failed to configure link: %d\n", err);
740 return err;
744 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
746 if (err)
747 return err;
754 int err;
756 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
758 if (err)
759 return err;
762 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
764 if (err)
765 return err;
774 int err;
776 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
777 if (err < 0) {
778 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
779 return err;
782 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
784 if (err)
785 return err;
787 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
790 if (err)
791 return err;
793 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
795 if (err)
796 return err;
798 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
800 if (err)
801 return err;
809 int err;
811 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
812 if (err < 0) {
813 DRM_ERROR("Get sink count failed %d\n", err);
814 return err;
828 int err, num_modes = 0;
838 err = anx78xx_get_downstream_info(anx78xx);
839 if (err) {
840 DRM_ERROR("Failed to get downstream info: %d\n", err);
850 err = drm_connector_update_edid_property(connector,
852 if (err) {
853 DRM_ERROR("Failed to update EDID property: %d\n", err);
893 int err;
911 err = drm_dp_aux_register(&anx78xx->aux);
912 if (err < 0) {
913 DRM_ERROR("Failed to register aux channel: %d\n", err);
914 return err;
917 err = drm_connector_init(bridge->dev, &anx78xx->connector,
920 if (err) {
921 DRM_ERROR("Failed to initialize connector: %d\n", err);
930 err = drm_connector_attach_encoder(&anx78xx->connector,
932 if (err) {
933 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
937 err = drm_connector_register(&anx78xx->connector);
938 if (err) {
939 DRM_ERROR("Failed to register connector: %d\n", err);
948 return err;
986 int err;
993 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
996 if (err) {
997 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1001 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1002 if (err)
1003 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1012 int err;
1014 err = anx78xx_start(anx78xx);
1015 if (err) {
1016 DRM_ERROR("Failed to initialize: %d\n", err);
1020 err = anx78xx_set_hpd(anx78xx);
1021 if (err)
1022 DRM_ERROR("Failed to set HPD: %d\n", err);
1037 int err;
1047 err = anx78xx_enable_interrupts(anx78xx);
1048 if (err)
1049 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1058 int err;
1062 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1064 if (err)
1065 return err;
1069 err = anx78xx_config_dp_output(anx78xx);
1072 return err;
1078 int err;
1082 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1084 if (err) {
1085 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1107 int err;
1111 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1113 if (err) {
1114 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1121 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1123 if (err) {
1124 DRM_ERROR("Read system status reg failed: %d\n", err);
1138 err = anx78xx_dp_link_training(anx78xx);
1139 if (err)
1140 DRM_ERROR("Failed to start link training: %d\n", err);
1149 int err;
1153 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1155 if (err) {
1156 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1163 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1165 if (err) {
1167 err);
1178 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1180 if (err) {
1181 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1225 int err;
1240 err = anx78xx_init_pdata(anx78xx);
1241 if (err) {
1242 if (err != -EPROBE_DEFER)
1243 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1245 return err;
1268 err = PTR_ERR(i2c_dummy);
1270 i2c_addresses[i], err);
1278 err = PTR_ERR(anx78xx->map[i]);
1288 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1290 if (err)
1293 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1295 if (err)
1300 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1302 if (err)
1317 err = -ENODEV;
1321 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1325 if (err) {
1327 err);
1331 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1335 if (err) {
1336 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1355 return err;