Lines Matching defs:ast
46 struct ast_device *ast = to_ast_device(dev);
52 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
54 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
67 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
70 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
71 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
75 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
77 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
108 u32 ast_mindwm(struct ast_device *ast, u32 r)
110 return __ast_mindwm(ast->regs, r);
113 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
115 __ast_moutdwm(ast->regs, r, v);
146 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
150 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
151 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
154 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
156 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
160 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
161 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
164 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
166 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
170 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
171 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
176 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
181 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
184 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
186 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
190 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
191 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
196 static int cbrtest_ast2150(struct ast_device *ast)
201 if (mmctestburst2_ast2150(ast, i))
206 static int cbrscan_ast2150(struct ast_device *ast, int busw)
211 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
213 if (cbrtest_ast2150(ast))
223 static void cbrdlli_ast2150(struct ast_device *ast, int busw)
233 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
234 data = cbrscan_ast2150(ast, busw);
250 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
257 struct ast_device *ast = to_ast_device(dev);
262 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
265 if (IS_AST_GEN1(ast)) {
267 ast_write32(ast, 0xf004, 0x1e6e0000);
268 ast_write32(ast, 0xf000, 0x1);
269 ast_write32(ast, 0x10100, 0xa8);
273 } while (ast_read32(ast, 0x10100) != 0xa8);
275 if (ast->chip == AST2100 || ast->chip == AST2200)
280 ast_write32(ast, 0xf004, 0x1e6e0000);
281 ast_write32(ast, 0xf000, 0x1);
282 ast_write32(ast, 0x12000, 0x1688A8A8);
285 } while (ast_read32(ast, 0x12000) != 0x01);
287 ast_write32(ast, 0x10000, 0xfc600309);
290 } while (ast_read32(ast, 0x10000) != 0x01);
297 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
299 if (ast->dram_type == AST_DRAM_1Gx16)
301 else if (ast->dram_type == AST_DRAM_1Gx32)
304 temp = ast_read32(ast, 0x12070);
307 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
309 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
314 data = ast_read32(ast, 0x10120);
316 data = ast_read32(ast, 0x10004);
318 cbrdlli_ast2150(ast, 16); /* 16 bits */
320 cbrdlli_ast2150(ast, 32); /* 32 bits */
323 switch (AST_GEN(ast)) {
325 temp = ast_read32(ast, 0x10140);
326 ast_write32(ast, 0x10140, temp | 0x40);
330 temp = ast_read32(ast, 0x1200c);
331 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
332 temp = ast_read32(ast, 0x12040);
333 ast_write32(ast, 0x12040, temp | 0x40);
342 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
348 struct ast_device *ast = to_ast_device(dev);
352 if (IS_AST_GEN7(ast)) {
353 if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
355 } else if (ast->config_mode == ast_use_p2a) {
356 if (IS_AST_GEN6(ast))
358 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
365 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
366 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */
423 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
427 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
428 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
431 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
435 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
439 ast_moutdwm(ast, 0x1e6e0070, 0x0);
443 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
447 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
448 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
451 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
453 ast_moutdwm(ast, 0x1e6e0070, 0x0);
457 data = ast_mindwm(ast, 0x1e6e0078);
459 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
464 static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
466 return mmc_test(ast, datagen, 0xc1);
469 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
471 return mmc_test2(ast, datagen, 0x41);
474 static bool mmc_test_single(struct ast_device *ast, u32 datagen)
476 return mmc_test(ast, datagen, 0xc5);
479 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
481 return mmc_test2(ast, datagen, 0x05);
484 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
486 return mmc_test(ast, datagen, 0x85);
489 static int cbr_test(struct ast_device *ast)
493 data = mmc_test_single2(ast, 0);
497 data = mmc_test_burst2(ast, i);
508 static int cbr_scan(struct ast_device *ast)
514 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
516 if ((data = cbr_test(ast)) != 0) {
529 static u32 cbr_test2(struct ast_device *ast)
533 data = mmc_test_burst2(ast, 0);
536 data |= mmc_test_single2(ast, 0);
543 static u32 cbr_scan2(struct ast_device *ast)
549 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
551 if ((data = cbr_test2(ast)) != 0) {
564 static bool cbr_test3(struct ast_device *ast)
566 if (!mmc_test_burst(ast, 0))
568 if (!mmc_test_single(ast, 0))
573 static bool cbr_scan3(struct ast_device *ast)
578 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
580 if (cbr_test3(ast))
589 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
600 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
601 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
602 data = cbr_scan2(ast);
659 ast_moutdwm(ast, 0x1E6E0080, data);
684 ast_moutdwm(ast, 0x1E6E0084, data);
688 static void finetuneDQSI(struct ast_device *ast)
697 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
698 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
700 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
715 ast_moutdwm(ast, 0x1E6E000C, 0);
716 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
717 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
719 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
720 ast_moutdwm(ast, 0x1E6E0070, 0);
721 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
722 if (cbr_scan3(ast)) {
775 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
778 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
783 finetuneDQSI(ast);
784 if (finetuneDQI_L(ast, param) == false)
792 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
793 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
794 data = cbr_scan(ast);
830 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
834 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
838 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
841 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
855 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
883 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
913 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
943 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
957 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
971 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
987 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1005 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1023 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1076 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1081 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1082 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1083 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1084 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1086 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1087 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1089 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1092 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1093 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1094 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1095 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1096 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1097 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1098 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1099 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1100 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1101 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1102 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1103 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1104 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1105 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1106 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1107 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1108 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1109 ast_moutdwm(ast, 0x1E6E0054, 0);
1110 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1111 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1112 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1113 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1114 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1115 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1118 data = ast_mindwm(ast, 0x1E6E001C);
1120 data = ast_mindwm(ast, 0x1E6E001C);
1123 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1127 ast_moutdwm(ast, 0x1E6E0064, data2);
1133 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1136 ast_moutdwm(ast, 0x1E6E0068, data);
1138 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1140 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1141 ast_moutdwm(ast, 0x1E6E0018, data);
1143 ast_moutdwm(ast, 0x1E6E0018, data);
1145 data = ast_mindwm(ast, 0x1E6E001C);
1148 data = ast_mindwm(ast, 0x1E6E001C);
1151 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1152 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1153 ast_moutdwm(ast, 0x1E6E0018, data);
1155 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1156 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1159 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1160 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1161 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1162 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1163 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1164 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1165 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1166 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1167 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1169 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1177 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1180 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1183 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1186 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1187 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1189 data = ast_mindwm(ast, 0x1E6E0070);
1191 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1192 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1193 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1199 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1203 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1206 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1220 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1235 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1266 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1300 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1333 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1348 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1364 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1380 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1396 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1446 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1451 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1452 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1453 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1454 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1455 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1457 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1460 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1461 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1462 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1463 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1464 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1465 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1466 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1467 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1468 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1469 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1470 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1471 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1472 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1473 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1474 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1475 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1476 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1477 ast_moutdwm(ast, 0x1E6E0054, 0);
1478 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1479 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1480 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1481 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1482 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1483 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1487 data = ast_mindwm(ast, 0x1E6E001C);
1489 data = ast_mindwm(ast, 0x1E6E001C);
1492 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1496 ast_moutdwm(ast, 0x1E6E0064, data2);
1502 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1505 ast_moutdwm(ast, 0x1E6E0068, data);
1507 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1509 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1510 ast_moutdwm(ast, 0x1E6E0018, data);
1512 ast_moutdwm(ast, 0x1E6E0018, data);
1514 data = ast_mindwm(ast, 0x1E6E001C);
1517 data = ast_mindwm(ast, 0x1E6E001C);
1520 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1521 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1522 ast_moutdwm(ast, 0x1E6E0018, data);
1524 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1525 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1528 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1529 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1530 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1531 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1532 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1533 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1535 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1536 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1537 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1538 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1539 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1540 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1541 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1543 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1551 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1552 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1555 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1560 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1561 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1563 data = ast_mindwm(ast, 0x1E6E0070);
1565 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1566 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1567 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1574 struct ast_device *ast = to_ast_device(dev);
1579 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1581 ast_write32(ast, 0xf004, 0x1e6e0000);
1582 ast_write32(ast, 0xf000, 0x1);
1583 ast_write32(ast, 0x12000, 0x1688a8a8);
1586 } while (ast_read32(ast, 0x12000) != 0x1);
1588 ast_write32(ast, 0x10000, 0xfc600309);
1591 } while (ast_read32(ast, 0x10000) != 0x1);
1594 temp = ast_read32(ast, 0x12008);
1596 ast_write32(ast, 0x12008, temp);
1600 temp = ast_mindwm(ast, 0x1e6e2070);
1638 get_ddr3_info(ast, ¶m);
1639 ddr3_init(ast, ¶m);
1641 get_ddr2_info(ast, ¶m);
1642 ddr2_init(ast, ¶m);
1645 temp = ast_mindwm(ast, 0x1e6e2040);
1646 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1651 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1655 static bool cbr_test_2500(struct ast_device *ast)
1657 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1658 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1659 if (!mmc_test_burst(ast, 0))
1661 if (!mmc_test_single_2500(ast, 0))
1666 static bool ddr_test_2500(struct ast_device *ast)
1668 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1669 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1670 if (!mmc_test_burst(ast, 0))
1672 if (!mmc_test_burst(ast, 1))
1674 if (!mmc_test_burst(ast, 2))
1676 if (!mmc_test_burst(ast, 3))
1678 if (!mmc_test_single_2500(ast, 0))
1683 static void ddr_init_common_2500(struct ast_device *ast)
1685 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1686 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1687 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1688 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1689 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1690 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1691 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1692 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1693 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1694 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1695 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1696 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1697 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1698 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1699 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1700 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1701 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1702 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1703 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1706 static void ddr_phy_init_2500(struct ast_device *ast)
1711 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1714 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1719 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1724 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1726 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1730 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1740 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1744 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1745 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1747 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1748 ast_moutdwm(ast, 0x90100000, 0x35363738);
1749 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1750 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1753 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1757 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1761 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1767 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1768 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1771 static void enable_cache_2500(struct ast_device *ast)
1775 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1776 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1779 data = ast_mindwm(ast, 0x1E6E0004);
1781 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1784 static void set_mpll_2500(struct ast_device *ast)
1789 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1790 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1792 ast_moutdwm(ast, addr, 0x0);
1795 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1797 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1798 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1802 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1807 ast_moutdwm(ast, 0x1E6E2020, param);
1811 static void reset_mmc_2500(struct ast_device *ast)
1813 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1814 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1815 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1816 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1818 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1819 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1822 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1825 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1826 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1827 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1828 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1829 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1830 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1831 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1832 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1835 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1836 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1837 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1838 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1839 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1840 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1841 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1842 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1843 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1844 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1845 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1846 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1847 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1848 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1851 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1854 ddr_phy_init_2500(ast);
1856 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1857 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1858 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1860 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1861 enable_cache_2500(ast);
1862 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1863 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1866 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1873 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1874 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1875 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1876 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1877 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1878 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1879 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1880 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1883 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1884 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1885 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1886 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1887 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1888 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1889 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1890 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1891 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1892 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1893 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1894 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1895 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1896 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1897 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1900 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1908 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1910 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1911 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1912 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1914 ddr_phy_init_2500(ast);
1915 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1916 if (cbr_test_2500(ast)) {
1918 data = ast_mindwm(ast, 0x1E6E03D0);
1931 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1941 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1942 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1943 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1945 ddr_phy_init_2500(ast);
1946 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1947 if (cbr_test_2500(ast)) {
1958 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1959 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1961 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1964 ddr_phy_init_2500(ast);
1966 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1967 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1968 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1970 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1971 enable_cache_2500(ast);
1972 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1973 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1976 static bool ast_dram_init_2500(struct ast_device *ast)
1984 set_mpll_2500(ast);
1985 reset_mmc_2500(ast);
1986 ddr_init_common_2500(ast);
1988 data = ast_mindwm(ast, 0x1E6E2070);
1990 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1992 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1993 } while (!ddr_test_2500(ast));
1995 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1998 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1999 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2043 struct ast_device *ast = to_ast_device(dev);
2047 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2050 ast_patch_ahb_2500(ast->regs);
2053 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2054 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2069 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2070 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2071 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2072 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2074 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2077 temp = ast_mindwm(ast, 0x1E6E2070);
2079 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2082 temp = ast_read32(ast, 0x12008);
2084 ast_write32(ast, 0x12008, temp);
2086 if (!ast_dram_init_2500(ast))
2089 temp = ast_mindwm(ast, 0x1e6e2040);
2090 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2095 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);