pm/swsmu/smu_cmn.c

50 #define smu_cmn_call_asic_func(intf, smu, args...)                             \
51 	((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ?                          \
52 				     (smu)->ppt_funcs->intf(smu, ##args) :     \
56 static const char *smu_get_message_name(struct smu_context *smu,
60 		return "unknown smu message";
65 static void smu_cmn_read_arg(struct smu_context *smu,
68 	struct amdgpu_device *adev = smu->adev;
70 	*arg = RREG32(smu->param_reg);
91  * @smu: a pointer to SMU context
109 static u32 __smu_cmn_poll_stat(struct smu_context *smu)
111 	struct amdgpu_device *adev = smu->adev;
116 		reg = RREG32(smu->resp_reg);
126 static void __smu_cmn_reg_print_error(struct smu_context *smu,
132 	struct amdgpu_device *adev = smu->adev;
133 	const char *message = smu_get_message_name(smu, msg);
138 		msg_idx = RREG32(smu->msg_reg);
139 		prm     = RREG32(smu->param_reg);
182 static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)
227 static void __smu_cmn_send_msg(struct smu_context *smu,
231 	struct amdgpu_device *adev = smu->adev;
233 	WREG32(smu->resp_reg, 0);
234 	WREG32(smu->param_reg, param);
235 	WREG32(smu->msg_reg, msg);
238 static int __smu_cmn_send_debug_msg(struct smu_context *smu,
242 	struct amdgpu_device *adev = smu->adev;
244 	WREG32(smu->debug_param_reg, param);
245 	WREG32(smu->debug_msg_reg, msg);
246 	WREG32(smu->debug_resp_reg, 0);
252  * @smu: pointer to an SMU context
263 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
267 	struct amdgpu_device *adev = smu->adev;
274 	reg = __smu_cmn_poll_stat(smu);
275 	res = __smu_cmn_reg2errno(smu, reg);
279 	__smu_cmn_send_msg(smu, msg_index, param);
293  * @smu: pointer to an SMU context
301 int smu_cmn_wait_for_response(struct smu_context *smu)
306 	reg = __smu_cmn_poll_stat(smu);
307 	res = __smu_cmn_reg2errno(smu, reg);
309 	if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
311 		amdgpu_device_halt(smu->adev);
320  * @smu: pointer to an SMU context
350 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
355 	struct amdgpu_device *adev = smu->adev;
362 	index = smu_cmn_to_asic_specific_index(smu,
368 	mutex_lock(&smu->message_lock);
369 	reg = __smu_cmn_poll_stat(smu);
370 	res = __smu_cmn_reg2errno(smu, reg);
373 		__smu_cmn_reg_print_error(smu, reg, index, param, msg);
376 	__smu_cmn_send_msg(smu, (uint16_t) index, param);
377 	reg = __smu_cmn_poll_stat(smu);
378 	res = __smu_cmn_reg2errno(smu, reg);
380 		__smu_cmn_reg_print_error(smu, reg, index, param, msg);
382 		smu_cmn_read_arg(smu, read_arg);
383 		dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x,\
385 			smu_get_message_name(smu, msg), index, param, reg, *read_arg);
387 		dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x\n",
388 			smu_get_message_name(smu, msg), index, param, reg);
396 	mutex_unlock(&smu->message_lock);
400 int smu_cmn_send_smc_msg(struct smu_context *smu,
404 	return smu_cmn_send_smc_msg_with_param(smu,
410 int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
413 	return __smu_cmn_send_debug_msg(smu, msg, 0);
416 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
419 	return __smu_cmn_send_debug_msg(smu, msg, param);
422 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
432 		    !smu->message_map)
435 		msg_mapping = smu->message_map[index];
439 		if (amdgpu_sriov_vf(smu->adev) &&
447 		    !smu->clock_map)
450 		mapping = smu->clock_map[index];
458 		    !smu->feature_map)
461 		mapping = smu->feature_map[index];
469 		    !smu->table_map)
472 		mapping = smu->table_map[index];
480 		    !smu->pwr_src_map)
483 		mapping = smu->pwr_src_map[index];
491 		    !smu->workload_map)
494 		mapping = smu->workload_map[index];
505 int smu_cmn_feature_is_supported(struct smu_context *smu,
508 	struct smu_feature *feature = &smu->smu_feature;
511 	feature_id = smu_cmn_to_asic_specific_index(smu,
522 static int __smu_get_enabled_features(struct smu_context *smu,
525 	return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
528 int smu_cmn_feature_is_enabled(struct smu_context *smu,
531 	struct amdgpu_device *adev = smu->adev;
535 	if (__smu_get_enabled_features(smu, &enabled_features)) {
548 	feature_id = smu_cmn_to_asic_specific_index(smu,
557 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
589 	if (!smu_cmn_feature_is_enabled(smu, feature_id))
595 int smu_cmn_get_enabled_mask(struct smu_context *smu,
608 	index = smu_cmn_to_asic_specific_index(smu,
612 		ret = smu_cmn_send_smc_msg_with_param(smu,
619 		ret = smu_cmn_send_smc_msg_with_param(smu,
624 		ret = smu_cmn_send_smc_msg(smu,
630 		ret = smu_cmn_send_smc_msg(smu,
651 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
658 		ret = smu_cmn_send_smc_msg_with_param(smu,
664 		ret = smu_cmn_send_smc_msg_with_param(smu,
669 		ret = smu_cmn_send_smc_msg_with_param(smu,
675 		ret = smu_cmn_send_smc_msg_with_param(smu,
684 int smu_cmn_feature_set_enabled(struct smu_context *smu,
690 	feature_id = smu_cmn_to_asic_specific_index(smu,
696 	return smu_cmn_feature_update_enable_state(smu,
707 static const char *smu_get_feature_name(struct smu_context *smu,
711 		return "unknown smu feature";
715 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
724 	if (__smu_get_enabled_features(smu, &feature_mask))
733 		feature_index = smu_cmn_to_asic_specific_index(smu,
751 				smu_get_feature_name(smu, sort_feature[feature_index]),
760 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
768 	ret = __smu_get_enabled_features(smu, &feature_mask);
776 		ret = smu_cmn_feature_update_enable_state(smu,
783 		ret = smu_cmn_feature_update_enable_state(smu,
798  * @smu:               smu_context pointer
806 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
813 		skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
822 	return smu_cmn_feature_update_enable_state(smu,
827 int smu_cmn_get_smc_version(struct smu_context *smu,
836 	if (smu->smc_fw_if_version && smu->smc_fw_version)
839 			*if_version = smu->smc_fw_if_version;
842 			*smu_version = smu->smc_fw_version;
848 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
852 		smu->smc_fw_if_version = *if_version;
856 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
860 		smu->smc_fw_version = *smu_version;
866 int smu_cmn_update_table(struct smu_context *smu,
872 	struct smu_table_context *smu_table = &smu->smu_table;
873 	struct amdgpu_device *adev = smu->adev;
875 	int table_id = smu_cmn_to_asic_specific_index(smu,
894 	ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
910 int smu_cmn_write_watermarks_table(struct smu_context *smu)
912 	void *watermarks_table = smu->smu_table.watermarks_table;
917 	return smu_cmn_update_table(smu,
924 int smu_cmn_write_pptable(struct smu_context *smu)
926 	void *pptable = smu->smu_table.driver_pptable;
928 	return smu_cmn_update_table(smu,
935 int smu_cmn_get_metrics_table(struct smu_context *smu,
939 	struct smu_table_context *smu_table = &smu->smu_table;
947 		ret = smu_cmn_update_table(smu,
953 			dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
965 int smu_cmn_get_combo_pptable(struct smu_context *smu)
967 	void *pptable = smu->smu_table.combo_pptable;
969 	return smu_cmn_update_table(smu,
1034 int smu_cmn_set_mp1_state(struct smu_context *smu,
1055 	ret = smu_cmn_send_smc_msg(smu, msg, NULL);
1057 		dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");